Skip to content
GitLab
Projects
Groups
Snippets
Help
Loading...
Help
Help
Support
Community forum
Keyboard shortcuts
?
Submit feedback
Contribute to GitLab
Sign in / Register
Toggle navigation
Open sidebar
Kestrel Collaboration
Kestrel LiteX
migen
Commits
8c01da61
Commit
8c01da61
authored
6 years ago
by
N. Engelhardt
Committed by
Sébastien Bourdeauducq
6 years ago
Browse files
Options
Download
Email Patches
Plain Diff
make memory simulation behavior for read ports same as emitted verilog
parent
b5d4f3f4
Changes
1
Hide whitespace changes
Inline
Side-by-side
Showing
1 changed file
with
1 addition
and
1 deletion
+1
-1
migen/fhdl/simplify.py
migen/fhdl/simplify.py
+1
-1
No files found.
migen/fhdl/simplify.py
View file @
8c01da61
...
...
@@ -87,7 +87,7 @@ class MemoryToArray(ModuleTransformer):
if
port
.
async_read
:
f
.
comb
.
append
(
port
.
dat_r
.
eq
(
storage
[
port
.
adr
]))
else
:
if
port
.
mode
==
WRITE_FIRST
and
port
.
we
is
not
None
:
if
port
.
mode
==
WRITE_FIRST
:
adr_reg
=
Signal
.
like
(
port
.
adr
)
rd_stmt
=
adr_reg
.
eq
(
port
.
adr
)
f
.
comb
.
append
(
port
.
dat_r
.
eq
(
storage
[
adr_reg
]))
...
...
This diff is collapsed.
Click to expand it.
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
.
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment