Commit 8c01da61 authored by N. Engelhardt's avatar N. Engelhardt Committed by Sébastien Bourdeauducq
Browse files

make memory simulation behavior for read ports same as emitted verilog

parent b5d4f3f4
......@@ -87,7 +87,7 @@ class MemoryToArray(ModuleTransformer):
if port.async_read:
f.comb.append(port.dat_r.eq(storage[port.adr]))
else:
if port.mode == WRITE_FIRST and port.we is not None:
if port.mode == WRITE_FIRST:
adr_reg = Signal.like(port.adr)
rd_stmt = adr_reg.eq(port.adr)
f.comb.append(port.dat_r.eq(storage[adr_reg]))
......
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