Tested with a CPU frequency of 70MHz and a nest frequency of 50MHz

EXPERIMENTAL, use at own risk!

Fix color decode logic

cores/Video: Expose fifo_depth and add underflow signal that can be used investigate bandwidth issues.

cores/video/VideoTerminal: Write CSI interpreter color to term_mem (\e[92;1m\e[0m decoding working).

cores/video/VideoTerminal: Also do a CLEAR-X after RST-X (Fix issue with lines displayed with previous contents).

Tested on Raptor Sparrowhawk

Tested to work on Raptor Sparrowhawk with IT66121 transceiver

This is Kestrel specific, NOT FOR UPSTREAM MERGE
Reduce main program load time from ~30s to ~3s

This adds additional protection and speeds up the
verification process significantly.

This functionality is only enabled on the Lattice+Trellis flow
for now.

All POWER systems have an architecturally defined decrementer and
timestamp counter.  On such systems, the LiteX timer peripheral
is redundant, but the LiteX BIOS assumes it is present on all SoCs.

Add a minimal interface from the LiteX BIOS code to the POWER
internal decrementer for SoCs without the LiteX timer peripheral.

Add Raptor ICLA See https://gitlab.raptorengineering.com/kestrel-collaboration/kestrel-litex/litex/-/wikis/CLA

Allow interrupts on Change, Rising Edge or Falling Edge.

cpu/vexriscv_smp add FPU support

liteeth: allow to specify nrxslots and ntxslots for liteeth

Compilation tested in Arty with:

from litex.soc.cores.gpio import GPIOIn
self.submodules.gpio_in = GPIOIn(platform.request("user_sw", 0), with_irq=True)
self.add_csr("gpio_in")
self.add_interrupt("gpio_in")

interconnect/axi: Fix AXILiteDownverterWrite/Read base address.

cores/video: Add VideoECP5HDMI PHY and move 10to1 Serializer to Generic, share it for Spartan6/ECP5.

Allow supporting all cases.

video: convenience method to add color bar pattern

software/liblitesdcard: Check sdcard_wait_data_done in sdcard_switch/sdcard_app_send_scr since requesting a data read transfer.