- 22 Apr, 2021 2 commits
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Raptor Engineering Development Team authoredThis is Kestrel specific, NOT FOR UPSTREAM MERGE Reduce main program load time from ~30s to ~3s
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Raptor Engineering Development Team authored
This adds additional protection and speeds up the verification process significantly.
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- 21 Apr, 2021 6 commits
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Raptor Engineering Development Team authored
This functionality is only enabled on the Lattice+Trellis flow for now.
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Raptor Engineering Development Team authored
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Raptor Engineering Development Team authored
All POWER systems have an architecturally defined decrementer and timestamp counter. On such systems, the LiteX timer peripheral is redundant, but the LiteX BIOS assumes it is present on all SoCs. Add a minimal interface from the LiteX BIOS code to the POWER internal decrementer for SoCs without the LiteX timer peripheral.
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Raptor Engineering Development Team authored
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Raptor Engineering Development Team authored
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- 20 Mar, 2021 1 commit
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Florent Kermarrec authoredAllow interrupts on Change, Rising Edge or Falling Edge.
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- 19 Mar, 2021 2 commits
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enjoy-digital authored
cpu/vexriscv_smp add FPU support
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enjoy-digital authored
liteeth: allow to specify nrxslots and ntxslots for liteeth
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- 18 Mar, 2021 7 commits
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Florent Kermarrec authored
Compilation tested in Arty with: from litex.soc.cores.gpio import GPIOIn self.submodules.gpio_in = GPIOIn(platform.request("user_sw", 0), with_irq=True) self.add_csr("gpio_in") self.add_interrupt("gpio_in") -
enjoy-digital authored
interconnect/axi: Fix AXILiteDownverterWrite/Read base address.
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Florent Kermarrec authored
cores/video: Add VideoECP5HDMI PHY and move 10to1 Serializer to Generic, share it for Spartan6/ECP5.
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
Allow supporting all cases.
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Marek Czerski authored
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- 17 Mar, 2021 1 commit
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Dolu1990 authored
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- 16 Mar, 2021 3 commits
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enjoy-digital authored
video: convenience method to add color bar pattern
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Florent Kermarrec authored
software/liblitesdcard: Check sdcard_wait_data_done in sdcard_switch/sdcard_app_send_scr since requesting a data read transfer.
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Hans Baier authored
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- 15 Mar, 2021 3 commits
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Florent Kermarrec authored
cores/xadc: Review/Cleanup PR#838, rename _XADC to SystemMonitorDRP and USSYSMON to USSystemMonitor.
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enjoy-digital authored
Ussysmon: SYSMONE1 for US devices
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Florent Kermarrec authored
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- 12 Mar, 2021 5 commits
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enjoy-digital authored
Add support for xcompiler on Alpine 3.13
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Benjamin Henrion authored
Problem: xcompiler on Alpine 3.13 was not found Solution is to add "riscv-none-elf-gcc": 1. Add Edge to your repositories: $ echo -e "http://dl-cdn.alpinelinux.org/alpine/edge/main\nhttp://dl-cdn.alpinelinux.org/alpine/edge/testing\nhttp://dl-cdn.alpine linux.org/alpine/edge/community" >> /etc/apk/repositories $ apk update $ apk add gcc-riscv-none-elf 2. The xcompiler should be found at: $ which riscv-none-elf-gcc /usr/bin/riscv-none-elf-gcc
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Florent Kermarrec authored
software/liblitedram: Improve find_cmd_delay to favor higher number of valid modules and centered scan. Also add an optional debug #define to look at cmd/clk centering scans: __ _ __ _ __ / / (_) /____ | |/_/ / /__/ / __/ -_)> < /____/_/\__/\__/_/|_| Build your hardware, easily! (c) Copyright 2012-2020 Enjoy-Digital (c) Copyright 2007-2015 M-Labs BIOS built on Mar 12 2021 14:06:20 BIOS CRC passed (116682af) Migen git sha1: 7014bdc LiteX git sha1: edcc0f88 --=============== SoC ==================-- CPU: VexRiscv @ 125MHz BUS: WISHBONE 32-bit @ 4GiB CSR: 32-bit data ROM: 64KiB SRAM: 8KiB L2: 8KiB SDRAM: 1048576KiB 64-bit @ 1000MT/s (CL-7 CWL-6) --========== Initialization ============-- Initializing SDRAM @0x40000000... Switching SDRAM to software control. Write leveling: tCK/4 taps: 6 Cmd/Clk scan (0-12) |Cmd/Clk delay: 0 m0: |11000000000000011111111111| delay: 15 m1: |00000000000000111111111111| delay: 14 m2: |11110000000000000111111111| delay: 17 m3: |11110000000000000011111111| delay: 18 m4: |11111111110000000000000111| delay: - m5: |11111111110000000000000111| delay: - m6: |11111111111000000000000001| delay: - m7: |11111111111000000000000011| delay: - Delay mean: 22, ideal: 13 Cmd/Clk delay: 1 m0: |11100000000000001111111111| delay: 16 m1: |10000000000000011111111111| delay: 15 m2: |11111000000000000011111111| delay: 18 m3: |11111000000000000001111111| delay: 19 m4: |11111111111000000000000011| delay: - m5: |11111111111000000000000011| delay: - m6: |11111111111100000000000000| delay: - m7: |11111111111100000000000001| delay: - Delay mean: 23, ideal: 13 Cmd/Clk delay: 2 m0: |11110000000000000111111111| delay: 17 m1: |11000000000000001111111111| delay: 16 m2: |11111100000000000001111111| delay: - m3: |11111100000000000000111111| delay: - m4: |11111111111100000000000001| delay: - m5: |11111111111100000000000001| delay: - m6: |11111111111110000000000000| delay: - m7: |11111111111110000000000000| delay: - Delay mean: 22, ideal: 13 Cmd/Clk delay: 3 m0: |11111000000000000011111111| delay: 18 m1: |11100000000000000111111111| delay: 17 m2: |11111110000000000000111111| delay: - m3: |11111110000000000000011111| delay: - m4: |11111111111110000000000000| delay: - m5: |11111111111110000000000000| delay: - m6: |01111111111111000000000000| delay: 01 m7: |01111111111111000000000000| delay: 01 Delay mean: 15, ideal: 13 Cmd/Clk delay: 4 m0: |11111100000000000001111111| delay: - m1: |11110000000000000011111111| delay: 18 m2: |11111111000000000000011111| delay: - m3: |11111111000000000000001111| delay: - m4: |11111111111111000000000000| delay: - m5: |11111111111111000000000000| delay: - m6: |00111111111111100000000000| delay: 02 m7: |00111111111111100000000000| delay: 02 Delay mean: 13, ideal: 13 Cmd/Clk delay: 5 m0: |11111110000000000000111111| delay: - m1: |11111000000000000001111111| delay: 19 m2: |11111111100000000000001111| delay: - m3: |11111111100000000000000111| delay: - m4: |01111111111111100000000000| delay: 01 m5: |01111111111111100000000000| delay: 01 m6: |00011111111111110000000000| delay: 03 m7: |00011111111111110000000000| delay: 03 Delay mean: 11, ideal: 13 Cmd/Clk delay: 6 m0: |11111111000000000000011111| delay: - m1: |11111100000000000000111111| delay: - m2: |11111111110000000000000111| delay: - m3: |11111111110000000000000011| delay: - m4: |00111111111111110000000000| delay: 02 m5: |00011111111111110000000000| delay: 03 m6: |00001111111111111000000000| delay: 04 m7: |00001111111111111000000000| delay: 04 Delay mean: 9, ideal: 13 Cmd/Clk delay: 7 m0: |11111111100000000000001111| delay: - m1: |11111110000000000000011111| delay: - m2: |11111111111000000000000011| delay: - m3: |11111111111000000000000001| delay: - m4: |00011111111111111000000000| delay: 03 m5: |00001111111111111000000000| delay: 04 m6: |00000111111111111100000000| delay: 05 m7: |00000111111111111100000000| delay: 05 Delay mean: 10, ideal: 13 Cmd/Clk delay: 8 m0: |11111111110000000000000111| delay: - m1: |11111111000000000000001111| delay: - m2: |11111111111100000000000001| delay: - m3: |11111111111100000000000000| delay: - m4: |00001111111111111100000000| delay: 04 m5: |00000111111111111100000000| delay: 05 m6: |00000011111111111110000000| delay: 06 m7: |00000011111111111110000000| delay: 06 Delay mean: 11, ideal: 13 Cmd/Clk delay: 9 m0: |11111111111000000000000011| delay: - m1: |11111111100000000000000111| delay: - m2: |11111111111110000000000000| delay: - m3: |11111111111110000000000000| delay: - m4: |00000111111111111110000000| delay: 05 m5: |00000011111111111110000000| delay: 06 m6: |00000001111111111111000000| delay: 07 m7: |00000001111111111111000000| delay: 07 Delay mean: 12, ideal: 13 Cmd/Clk delay: 10 m0: |11111111111100000000000011| delay: - m1: |11111111110000000000000011| delay: - m2: |01111111111111000000000000| delay: 01 m3: |01111111111111000000000000| delay: 01 m4: |00000011111111111111000000| delay: 06 m5: |00000001111111111111000000| delay: 07 m6: |00000000111111111111100000| delay: 08 m7: |00000000111111111111100000| delay: 08 Delay mean: 11, ideal: 13 Cmd/Clk delay: 11 m0: |11111111111110000000000001| delay: - m1: |11111111111000000000000001| delay: - m2: |00111111111111100000000000| delay: 02 m3: |00111111111111100000000000| delay: 02 m4: |00000001111111111111100000| delay: 07 m5: |00000000111111111111100000| delay: 08 m6: |00000000011111111111110000| delay: 09 m7: |00000000011111111111110000| delay: 09 Delay mean: 12, ideal: 13 | best: 11 Setting Cmd/Clk delay to 11 taps. Data scan: m0: |11111111111110000000000001| delay: - m1: |11111111111000000000000001| delay: - m2: |00111111111111100000000000| delay: 02 m3: |00111111111111100000000000| delay: 02 m4: |00000001111111111111100000| delay: 07 m5: |00000000111111111111100000| delay: 08 m6: |00000000011111111111110000| delay: 09 m7: |00000000011111111111110000| delay: 09 Write latency calibration: m0:6 m1:6 m2:6 m3:6 m4:6 m5:6 m6:6 m7:6 Read leveling: m0, b0: |00000000000000000000000000000000| delays: - m0, b1: |00000000000000000000000000000000| delays: - m0, b2: |00000000000000000000000000000000| delays: - m0, b3: |11111111100000000000000000000000| delays: 04+-04 m0, b4: |00000000000001111111110000000000| delays: 17+-04 m0, b5: |00000000000000000000000000111111| delays: 29+-03 m0, b6: |00000000000000000000000000000000| delays: - m0, b7: |00000000000000000000000000000000| delays: - best: m0, b03 delays: 04+-04 m1, b0: |00000000000000000000000000000000| delays: - m1, b1: |00000000000000000000000000000000| delays: - m1, b2: |00000000000000000000000000000000| delays: - m1, b3: |11111111000000000000000000000000| delays: 04+-04 m1, b4: |00000000000011111111100000000000| delays: 16+-04 m1, b5: |00000000000000000000000000111111| delays: 29+-03 m1, b6: |00000000000000000000000000000000| delays: - m1, b7: |00000000000000000000000000000000| delays: - best: m1, b04 delays: 16+-04 m2, b0: |00000000000000000000000000000000| delays: - m2, b1: |00000000000000000000000000000000| delays: - m2, b2: |00000000000000000000000000000000| delays: - m2, b3: |11111110000000000000000000000000| delays: 03+-03 m2, b4: |00000000000111111111000000000000| delays: 15+-04 m2, b5: |00000000000000000000000011111111| delays: 28+-04 m2, b6: |00000000000000000000000000000000| delays: - m2, b7: |00000000000000000000000000000000| delays: - best: m2, b04 delays: 15+-04 m3, b0: |00000000000000000000000000000000| delays: - m3, b1: |00000000000000000000000000000000| delays: - m3, b2: |00000000000000000000000000000000| delays: - m3, b3: |11111110000000000000000000000000| delays: 03+-03 m3, b4: |00000000001111111110000000000000| delays: 14+-04 m3, b5: |00000000000000000000000011111111| delays: 28+-04 m3, b6: |00000000000000000000000000000000| delays: - m3, b7: |00000000000000000000000000000000| delays: - best: m3, b04 delays: 14+-04 m4, b0: |00000000000000000000000000000000| delays: - m4, b1: |00000000000000000000000000000000| delays: - m4, b2: |00000000000000000000000000000000| delays: - m4, b3: |10000000000000000000000000000000| delays: - m4, b4: |00001111111110000000000000000000| delays: 08+-04 m4, b5: |00000000000000000111111111000000| delays: 22+-05 m4, b6: |00000000000000000000000000000001| delays: 31+-00 m4, b7: |00000000000000000000000000000000| delays: - best: m4, b04 delays: 08+-04 m5, b0: |00000000000000000000000000000000| delays: - m5, b1: |00000000000000000000000000000000| delays: - m5, b2: |00000000000000000000000000000000| delays: - m5, b3: |00000000000000000000000000000000| delays: - m5, b4: |00001111111110000000000000000000| delays: 08+-04 m5, b5: |00000000000000000011111111000000| delays: 22+-04 m5, b6: |00000000000000000000000000000001| delays: 31+-00 m5, b7: |00000000000000000000000000000000| delays: - best: m5, b04 delays: 08+-04 m6, b0: |00000000000000000000000000000000| delays: - m6, b1: |00000000000000000000000000000000| delays: - m6, b2: |00000000000000000000000000000000| delays: - m6, b3: |00000000000000000000000000000000| delays: - m6, b4: |00111111110000000000000000000000| delays: 06+-04 m6, b5: |00000000000000111111111000000000| delays: 18+-04 m6, b6: |00000000000000000000000000001111| delays: 30+-02 m6, b7: |00000000000000000000000000000000| delays: - best: m6, b05 delays: 19+-04 m7, b0: |00000000000000000000000000000000| delays: - m7, b1: |00000000000000000000000000000000| delays: - m7, b2: |00000000000000000000000000000000| delays: - m7, b3: |00000000000000000000000000000000| delays: - m7, b4: |01111111111100000000000000000000| delays: 06+-05 m7, b5: |00000000000000011111111110000000| delays: 20+-05 m7, b6: |00000000000000000000000000001111| delays: 30+-02 m7, b7: |00000000000000000000000000000000| delays: - best: m7, b04 delays: 06+-05 Switching SDRAM to hardware control. Memtest at 0x40000000 (2MiB)... Write: 0x40000000-0x40200000 2MiB Read: 0x40000000-0x40200000 2MiB Memtest OK Memspeed at 0x40000000 (2MiB)... Write speed: 40MiB/s Read speed: 33MiB/s --============== Boot ==================-- Booting from serial... Press Q or ESC to abort boot completely. sL5DdSMmkekro Timeout No boot medium found --============= Console ================-- -
Florent Kermarrec authored
soc: Add init_rom to initialize ROM and contents and with auto_size option (enable by default) to reduce ROM size to length of contents when in Read Only mode. This ensures the integrated ROM is reduced to minimal size before build and avoid having to adjust it manually with --integrated-rom-size on targets.
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Florent Kermarrec authored
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- 11 Mar, 2021 3 commits
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Florent Kermarrec authored
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enjoy-digital authored
xics: Disable endianness swapping
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Florent Kermarrec authored
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- 10 Mar, 2021 7 commits
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Florent Kermarrec authored
Useful for standalone core where the user logic can be looking at init_done/init_error to condition user accesses.
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Florent Kermarrec authored
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Florent Kermarrec authored
Downconverter should start on master's addr, not on aligned master's addr.
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Evan Lojewski authored
The endianess swapping code caused the core to diverge from microwatt resulting in: - The xics tests not working as-is: https://github.com/antonblanchard/microwatt/blob/master/tests/xics/xics.h - byte writes writing to the incorrect byte This removes endianswapping and minimizes the delta from upstream for the xics irq.h header.
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Evan Lojewski authored
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Florent Kermarrec authored
build/generic_platform: Make sure default_clk_period constraint is only applied when default_clk_period exists. In simulation, default_clk_period is not necessarily required.
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enjoy-digital authored
cores/stream/monitor: Fix typo
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