- 08 May, 2025 1 commit
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Raptor Engineering Development Team authored
This improves overall timing results with Microwatt enabled designs
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- 30 Apr, 2025 2 commits
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Raptor Engineering Development Team authored
On larger systems (32 bit or higher Wishbone data busses), using an 8 bit wide identifier RAM can result in significant higher resource consumption for additional decoding. Allow this to be configured on a board level basis.
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Raptor Engineering Development Team authored
This restores fmax lost with latest Yosys / NextPNR versions
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- 28 Apr, 2025 1 commit
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Raptor Engineering Development Team authored
Yosys optimizes the small ROM with the build identifier strings to flip flop logic vs. a block RAM by default, which causes the logic routing from Yosys to change on each build. Force this small ROM (mem_1) to block RAM to restore deterministic build behavior.
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- 27 Apr, 2025 3 commits
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Raptor Engineering Development Team authored
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Raptor Engineering Development Team authored
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Raptor Engineering Development Team authored
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- 25 Apr, 2025 3 commits
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Raptor Engineering Development Team authored
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Raptor Engineering Development Team authored
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Raptor Engineering Development Team authored
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- 24 Apr, 2025 1 commit
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Raptor Engineering Development Team authored
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- 15 Apr, 2025 2 commits
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Raptor Engineering Development Team authored
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Raptor Engineering Development Team authored
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- 14 Apr, 2025 1 commit
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Raptor Engineering Development Team authored
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- 12 Oct, 2024 2 commits
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Raptor Engineering Development Team authored
Reconfigure Kestrel on-module Flash controller to high speed mode instead of external BMC Flash controller This fixes slow boot from Flash with the current Kestrel Flash mapping
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Raptor Engineering Development Team authored
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- 06 Oct, 2024 1 commit
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Raptor Engineering Development Team authored
Wire watchdog in to master SoC reset line
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- 04 Oct, 2024 2 commits
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Raptor Engineering Development Team authored
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Raptor Engineering Development Team authored
NOTE: The TRNG remains disabled, and DARN will return an error status, due to limitations in NextPNR. This will be addressed in future work, but software that calls DARN will no longer encounter an illegal instruction trap.
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- 28 Sep, 2024 1 commit
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Raptor Engineering Development Team authored
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- 23 Sep, 2024 1 commit
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Raptor Engineering Development Team authored
This allows calculation of baud rates even when the core and nest clocks differ.
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- 12 Sep, 2024 1 commit
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Raptor Engineering Development Team authored
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- 19 Apr, 2023 2 commits
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Raptor Engineering Development Team authored
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Raptor Engineering Development Team authored
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- 17 Jan, 2023 3 commits
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Raptor Engineering Development Team authored
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Raptor Engineering Development Team authored
Tested with a CPU frequency of 70MHz and a nest frequency of 50MHz
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Raptor Engineering Development Team authored
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- 01 Jan, 2023 1 commit
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Raptor Engineering Development Team authored
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- 25 Dec, 2022 1 commit
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Raptor Engineering Development Team authored
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- 05 Jul, 2022 2 commits
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Raptor Engineering Development Team authored
EXPERIMENTAL, use at own risk!
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Raptor Engineering Development Team authored
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- 29 May, 2022 2 commits
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Raptor Engineering Development Team authored
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Raptor Engineering Development Team authored
Fix color decode logic
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- 28 May, 2022 5 commits
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Florent Kermarrec authored
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Florent Kermarrec authored
cores/Video: Expose fifo_depth and add underflow signal that can be used investigate bandwidth issues.
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Florent Kermarrec authored
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Florent Kermarrec authored
cores/video/VideoTerminal: Write CSI interpreter color to term_mem (\e[92;1m\e[0m decoding working).
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Florent Kermarrec authored
cores/video/VideoTerminal: Also do a CLEAR-X after RST-X (Fix issue with lines displayed with previous contents).
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- 18 May, 2022 1 commit
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Raptor Engineering Development Team authored
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- 04 Oct, 2021 1 commit
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Raptor Engineering Development Team authored
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