- 12 Oct, 2024 2 commits
-
-
Raptor Engineering Development Team authored
Reconfigure Kestrel on-module Flash controller to high speed mode instead of external BMC Flash controller This fixes slow boot from Flash with the current Kestrel Flash mapping
-
Raptor Engineering Development Team authored
-
- 06 Oct, 2024 1 commit
-
-
Raptor Engineering Development Team authored
Wire watchdog in to master SoC reset line
-
- 04 Oct, 2024 2 commits
-
-
Raptor Engineering Development Team authored
-
Raptor Engineering Development Team authored
NOTE: The TRNG remains disabled, and DARN will return an error status, due to limitations in NextPNR. This will be addressed in future work, but software that calls DARN will no longer encounter an illegal instruction trap.
-
- 28 Sep, 2024 1 commit
-
-
Raptor Engineering Development Team authored
-
- 23 Sep, 2024 1 commit
-
-
Raptor Engineering Development Team authored
This allows calculation of baud rates even when the core and nest clocks differ.
-
- 12 Sep, 2024 1 commit
-
-
Raptor Engineering Development Team authored
-
- 19 Apr, 2023 2 commits
-
-
Raptor Engineering Development Team authored
-
Raptor Engineering Development Team authored
-
- 17 Jan, 2023 3 commits
-
-
Raptor Engineering Development Team authored
-
Raptor Engineering Development Team authored
Tested with a CPU frequency of 70MHz and a nest frequency of 50MHz
-
Raptor Engineering Development Team authored
-
- 01 Jan, 2023 1 commit
-
-
Raptor Engineering Development Team authored
-
- 25 Dec, 2022 1 commit
-
-
Raptor Engineering Development Team authored
-
- 05 Jul, 2022 2 commits
-
-
Raptor Engineering Development Team authored
EXPERIMENTAL, use at own risk!
-
Raptor Engineering Development Team authored
-
- 29 May, 2022 2 commits
-
-
Raptor Engineering Development Team authored
-
Raptor Engineering Development Team authored
Fix color decode logic
-
- 28 May, 2022 5 commits
-
-
Florent Kermarrec authored
-
Florent Kermarrec authored
cores/Video: Expose fifo_depth and add underflow signal that can be used investigate bandwidth issues.
-
Florent Kermarrec authored
-
Florent Kermarrec authored
cores/video/VideoTerminal: Write CSI interpreter color to term_mem (\e[92;1m\e[0m decoding working).
-
Florent Kermarrec authored
cores/video/VideoTerminal: Also do a CLEAR-X after RST-X (Fix issue with lines displayed with previous contents).
-
- 18 May, 2022 1 commit
-
-
Raptor Engineering Development Team authored
-
- 04 Oct, 2021 1 commit
-
-
Raptor Engineering Development Team authored
-
- 07 Jun, 2021 2 commits
-
-
Raptor Engineering Development Team authored
Tested on Raptor Sparrowhawk
-
Raptor Engineering Development Team authored
Tested to work on Raptor Sparrowhawk with IT66121 transceiver
-
- 22 Apr, 2021 2 commits
-
-
Raptor Engineering Development Team authored
This is Kestrel specific, NOT FOR UPSTREAM MERGE Reduce main program load time from ~30s to ~3s
-
Raptor Engineering Development Team authored
This adds additional protection and speeds up the verification process significantly.
-
- 21 Apr, 2021 6 commits
-
-
Raptor Engineering Development Team authored
This functionality is only enabled on the Lattice+Trellis flow for now.
-
Raptor Engineering Development Team authored
-
Raptor Engineering Development Team authored
All POWER systems have an architecturally defined decrementer and timestamp counter. On such systems, the LiteX timer peripheral is redundant, but the LiteX BIOS assumes it is present on all SoCs. Add a minimal interface from the LiteX BIOS code to the POWER internal decrementer for SoCs without the LiteX timer peripheral.
-
Raptor Engineering Development Team authored
-
Raptor Engineering Development Team authored
-
- 20 Mar, 2021 1 commit
-
-
Florent Kermarrec authored
Allow interrupts on Change, Rising Edge or Falling Edge.
-
- 19 Mar, 2021 2 commits
-
-
enjoy-digital authored
cpu/vexriscv_smp add FPU support
-
enjoy-digital authored
liteeth: allow to specify nrxslots and ntxslots for liteeth
-
- 18 Mar, 2021 1 commit
-
-
Florent Kermarrec authored
Compilation tested in Arty with: from litex.soc.cores.gpio import GPIOIn self.submodules.gpio_in = GPIOIn(platform.request("user_sw", 0), with_irq=True) self.add_csr("gpio_in") self.add_interrupt("gpio_in")
-