GitLab

This improves overall timing results with Microwatt enabled designs

On larger systems (32 bit or higher Wishbone data busses), using an 8 bit wide
identifier RAM can result in significant higher resource consumption for
additional decoding.  Allow this to be configured on a board level basis.

This restores fmax lost with latest Yosys / NextPNR versions

Yosys optimizes the small ROM with the build identifier strings to
flip flop logic vs. a block RAM by default, which causes the logic
routing from Yosys to change on each build.

Force this small ROM (mem_1) to block RAM to restore deterministic
build behavior.

Reconfigure Kestrel on-module Flash controller to high speed mode instead of external BMC Flash controller

This fixes slow boot from Flash with the current Kestrel Flash mapping

Wire watchdog in to master SoC reset line

NOTE: The TRNG remains disabled, and DARN will return an error
status, due to limitations in NextPNR.  This will be addressed
in future work, but software that calls DARN will no longer encounter
an illegal instruction trap.

This allows calculation of baud rates even when the core
and nest clocks differ.

Tested with a CPU frequency of 70MHz and a nest frequency of 50MHz

EXPERIMENTAL, use at own risk!

Fix color decode logic

cores/Video: Expose fifo_depth and add underflow signal that can be used investigate bandwidth issues.

cores/video/VideoTerminal: Write CSI interpreter color to term_mem (\e[92;1m\e[0m decoding working).

cores/video/VideoTerminal: Also do a CLEAR-X after RST-X (Fix issue with lines displayed with previous contents).