mercury_xu5.py 4.6 KB
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#!/usr/bin/env python3

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#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2020 Antmicro <www.antmicro.com>
# SPDX-License-Identifier: BSD-2-Clause
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import os
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import argparse

from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex_boards.platforms import mercury_xu5

from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litedram.modules import MT40A256M16
from litedram.phy import usddrphy

# CRG ----------------------------------------------------------------------------------------------

class _CRG(Module):
    def __init__(self, platform, sys_clk_freq):
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        self.rst = Signal()
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        self.clock_domains.cd_sys    = ClockDomain()
        self.clock_domains.cd_sys4x  = ClockDomain(reset_less=True)
        self.clock_domains.cd_pll4x  = ClockDomain(reset_less=True)
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        self.clock_domains.cd_idelay = ClockDomain()
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        # # #
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        self.submodules.pll = pll = USMMCM(speedgrade=-1)
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        self.comb += pll.reset.eq(self.rst)
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        pll.register_clkin(platform.request("clk100"), 100e6)

        pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False)
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        pll.create_clkout(self.cd_idelay, 500e6, with_reset=False)
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        self.specials += [
            Instance("BUFGCE_DIV", name="main_bufgce_div",
                p_BUFGCE_DIVIDE=4,
                i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys.clk),
            Instance("BUFGCE", name="main_bufgce",
                i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys4x.clk),
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            AsyncResetSynchronizer(self.cd_idelay, ~pll.locked),
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        ]

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        self.submodules.idelayctrl = USIDELAYCTRL(cd_ref=self.cd_idelay, cd_sys=self.cd_sys)
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# BaseSoC ------------------------------------------------------------------------------------------

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class BaseSoC(SoCCore):
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    def __init__(self, sys_clk_freq=int(125e6), **kwargs):
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        platform = mercury_xu5.Platform()

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        # SoCCore ----------------------------------------------------------------------------------
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        SoCCore.__init__(self, platform, sys_clk_freq,
            ident          = "LiteX SoC on Mercury XU5",
            ident_version  = True,
            **kwargs)
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        # CRG --------------------------------------------------------------------------------------
        self.submodules.crg = _CRG(platform, sys_clk_freq)

        # DDR4 SDRAM -------------------------------------------------------------------------------
        if not self.integrated_main_ram_size:
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            self.submodules.ddrphy = usddrphy.USPDDRPHY(platform.request("ddram"),
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                memtype          = "DDR4",
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                sys_clk_freq     = sys_clk_freq,
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                iodelay_clk_freq = 500e6,
                cmd_latency      = 0)
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            self.add_csr("ddrphy")
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            self.add_sdram("sdram",
                phy                     = self.ddrphy,
                module                  = MT40A256M16(sys_clk_freq, "1:4"),
                origin                  = self.mem_map["main_ram"],
                size                    = kwargs.get("max_sdram_size", 0x40000000),
                l2_cache_size           = kwargs.get("l2_size", 8192),
                l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
                l2_cache_reverse        = True
            )
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        # Leds -------------------------------------------------------------------------------------
        self.submodules.leds = LedChaser(
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            pads         = platform.request_all("user_led"),
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            sys_clk_freq = sys_clk_freq)
        self.add_csr("leds")

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# Build --------------------------------------------------------------------------------------------

def main():
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    parser = argparse.ArgumentParser(description="LiteX SoC on Mercury XU5")
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    parser.add_argument("--build",        action="store_true", help="Build bitstream")
    parser.add_argument("--load",         action="store_true", help="Load bitstream")
    parser.add_argument("--sys-clk-freq", default=125e6,       help="System clock frequency (default: 125MHz)")
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    builder_args(parser)
    soc_sdram_args(parser)
    args = parser.parse_args()

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    soc = BaseSoC(
         sys_clk_freq = int(float(args.sys_clk_freq)),
         **soc_sdram_argdict(args)
    )
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    builder = Builder(soc, **builder_argdict(args))
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    builder.build(run=args.build)
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    if args.load:
        prog = soc.platform.create_programmer()
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        prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
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if __name__ == "__main__":
    main()