Skip to content
GitLab
Projects
Groups
Snippets
Help
Loading...
Help
Help
Support
Community forum
Keyboard shortcuts
?
Submit feedback
Contribute to GitLab
Sign in / Register
Toggle navigation
Open sidebar
Kestrel Collaboration
Kestrel LiteX
litex-boards
Commits
ce38cff4
Commit
ce38cff4
authored
4 years ago
by
Jędrzej Boczar
Browse files
Options
Download
Email Patches
Plain Diff
mercury_xu5: reduce cmd_latency to fix problems with DRAM leveling
parent
a2f3add2
Changes
1
Hide whitespace changes
Inline
Side-by-side
Showing
1 changed file
with
2 additions
and
1 deletion
+2
-1
litex_boards/targets/mercury_xu5.py
litex_boards/targets/mercury_xu5.py
+2
-1
No files found.
litex_boards/targets/mercury_xu5.py
View file @
ce38cff4
...
...
@@ -73,7 +73,8 @@ class BaseSoC(SoCCore):
self
.
submodules
.
ddrphy
=
usddrphy
.
USPDDRPHY
(
platform
.
request
(
"ddram"
),
memtype
=
"DDR4"
,
sys_clk_freq
=
sys_clk_freq
,
iodelay_clk_freq
=
500e6
)
iodelay_clk_freq
=
500e6
,
cmd_latency
=
0
)
self
.
add_csr
(
"ddrphy"
)
self
.
add_sdram
(
"sdram"
,
phy
=
self
.
ddrphy
,
...
...
This diff is collapsed.
Click to expand it.
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
.
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment