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  • write_latency
    871c5efa · Fix bug where data is latched too early · Oct 04, 2018
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  • bank_reordering
    055cbdbc · tRRD is specified incorrectly. · Oct 11, 2018
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  • s7ddrphy_memory_mode
    759701c0 · phy/s7ddrphy: add half_sys8x delay on dqs_i · Nov 24, 2018
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  • bios-libs merged
    fe48a929 · test/reference: update. · May 19, 2020
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  • gh-pages
    657fe859 · Deploy enjoy-digital/litedram to github.com/enjoy-digital/litedram.git:gh-pages · Jun 10, 2020
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  • master default protected
    f17037fd · bench/common: Cleanup, Increase sys_clk measure time to 5s. · Mar 12, 2021
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  • ecp5ddr1x
    2dd30649 · Add option to switch ECP5 DDR3 clock/addr/cmd signals to ODDRX1F · Jun 02, 2021
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