Commit fe48a929 authored by Florent Kermarrec's avatar Florent Kermarrec

test/reference: update.

parent c30910a9
......@@ -450,11 +450,13 @@ def get_sdram_phy_c_header(phy_settings, timing_settings):
r = "#ifndef __GENERATED_SDRAM_PHY_H\n#define __GENERATED_SDRAM_PHY_H\n"
r += "#include <hw/common.h>\n"
r += "#include <generated/csr.h>\n"
r += "\n"
r += "#define DFII_CONTROL_SEL 0x01\n"
r += "#define DFII_CONTROL_CKE 0x02\n"
r += "#define DFII_CONTROL_ODT 0x04\n"
r += "#define DFII_CONTROL_RESET_N 0x08\n"
r += "\n"
r += "#define DFII_COMMAND_CS 0x01\n"
r += "#define DFII_COMMAND_WE 0x02\n"
......@@ -462,6 +464,7 @@ def get_sdram_phy_c_header(phy_settings, timing_settings):
r += "#define DFII_COMMAND_RAS 0x08\n"
r += "#define DFII_COMMAND_WRDATA 0x10\n"
r += "#define DFII_COMMAND_RDDATA 0x20\n"
r += "\n"
phytype = phy_settings.phytype.upper()
nphases = phy_settings.nphases
......
......@@ -2,7 +2,18 @@
#define __GENERATED_SDRAM_PHY_H
#include <hw/common.h>
#include <generated/csr.h>
#include <hw/flags.h>
#define DFII_CONTROL_SEL 0x01
#define DFII_CONTROL_CKE 0x02
#define DFII_CONTROL_ODT 0x04
#define DFII_CONTROL_RESET_N 0x08
#define DFII_COMMAND_CS 0x01
#define DFII_COMMAND_WE 0x02
#define DFII_COMMAND_CAS 0x04
#define DFII_COMMAND_RAS 0x08
#define DFII_COMMAND_WRDATA 0x10
#define DFII_COMMAND_RDDATA 0x20
#define SDRAM_PHY_K7DDRPHY
#define SDRAM_PHY_PHASES 4
......
......@@ -2,7 +2,18 @@
#define __GENERATED_SDRAM_PHY_H
#include <hw/common.h>
#include <generated/csr.h>
#include <hw/flags.h>
#define DFII_CONTROL_SEL 0x01
#define DFII_CONTROL_CKE 0x02
#define DFII_CONTROL_ODT 0x04
#define DFII_CONTROL_RESET_N 0x08
#define DFII_COMMAND_CS 0x01
#define DFII_COMMAND_WE 0x02
#define DFII_COMMAND_CAS 0x04
#define DFII_COMMAND_RAS 0x08
#define DFII_COMMAND_WRDATA 0x10
#define DFII_COMMAND_RDDATA 0x20
#define SDRAM_PHY_USDDRPHY
#define SDRAM_PHY_PHASES 4
......
......@@ -2,7 +2,18 @@
#define __GENERATED_SDRAM_PHY_H
#include <hw/common.h>
#include <generated/csr.h>
#include <hw/flags.h>
#define DFII_CONTROL_SEL 0x01
#define DFII_CONTROL_CKE 0x02
#define DFII_CONTROL_ODT 0x04
#define DFII_CONTROL_RESET_N 0x08
#define DFII_COMMAND_CS 0x01
#define DFII_COMMAND_WE 0x02
#define DFII_COMMAND_CAS 0x04
#define DFII_COMMAND_RAS 0x08
#define DFII_COMMAND_WRDATA 0x10
#define DFII_COMMAND_RDDATA 0x20
#define SDRAM_PHY_GENSDRPHY
#define SDRAM_PHY_PHASES 1
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment