1. 06 Jul, 2022 1 commit
  2. 05 Jul, 2022 1 commit
  3. 04 Jul, 2022 2 commits
  4. 26 Jun, 2022 6 commits
  5. 23 May, 2022 1 commit
  6. 01 May, 2022 1 commit
  7. 30 Apr, 2022 4 commits
    • Luke Kenneth Casson Leighton's avatar
      add missing module · ea854f5d
      Luke Kenneth Casson Leighton authored
      ea854f5d
    • Luke Kenneth Casson Leighton's avatar
      split off CR0/XER production in DIV Function Unit into separate stage · 67e177bf
      Luke Kenneth Casson Leighton authored
      due to massive combinatorial chains
      67e177bf
    • Luke Kenneth Casson Leighton's avatar
      clear out DEC in core.cur_state.dec due to spurious interrupt. · 972f7cdd
      Luke Kenneth Casson Leighton authored
      this is slightly complicated.  the STATE regfile contains pc, msr, svstate,
      dec, and tb, being a reflection of CoreState.  reading from STATE regfile
      is on a one-clock delay. the DEC/TB FSM needs to decrement DEC and increment
      TB, by reading from the STATE regfile and then writing a new value.
      
      of course, the SPR pipeline has to get a word in edgeways as well.
      
      but...
      
      the complication comes in that it is the PowerDecoder2 which receives
      a *cached* copy of DEC, and this cached copy is what has (up until now)
      been out-of-date with what is in the STATE regfile.
      
      the hack-job-solution is to zero-out the cached copy when the SPR pipeline
      writes a new value to DEC.  the DEC/TB FSM will then rewrite a correct
      value into it.
      
      given that PowerDecoder2 only uses the MSB of DEC (and the EE bit of MSR)
      to determine whether to fire an interrupt, this should be perfectly fine.
      972f7cdd
    • Cesar Strauss's avatar
      Implement transparent read port option on the XOR wrapper SRAM · e19eeb30
      Cesar Strauss authored
      Add a bypass path when simultaneously reading and writing to the same
      address.
      There needs to be an independent Mux for each write lane, since we may not be
      writing on all lanes, necessarily.
      e19eeb30
  8. 29 Apr, 2022 5 commits
  9. 28 Apr, 2022 7 commits
  10. 27 Apr, 2022 7 commits
  11. 26 Apr, 2022 2 commits
  12. 25 Apr, 2022 2 commits
  13. 23 Apr, 2022 1 commit