- 06 Jul, 2022 1 commit
-
-
Raptor Engineering Development Team authored
-
- 05 Jul, 2022 1 commit
-
-
Luke Kenneth Casson Leighton authored
meaning that mulhd is truncated (always zero) https://bugs.libre-soc.org/show_bug.cgi?id=855
-
- 04 Jul, 2022 2 commits
-
-
Luke Kenneth Casson Leighton authored
-
Luke Kenneth Casson Leighton authored
-
- 26 Jun, 2022 6 commits
-
-
Luke Kenneth Casson Leighton authored
into top bits
-
Luke Kenneth Casson Leighton authored
by redirecting OP_MTSPR and OP_MFSPR to it https://bugs.libre-soc.org/show_bug.cgi?id=859
-
Luke Kenneth Casson Leighton authored
-
Luke Kenneth Casson Leighton authored
-
Luke Kenneth Casson Leighton authored
-
Luke Kenneth Casson Leighton authored
(like alu test_pipe_caller.py)
-
- 23 May, 2022 1 commit
-
-
Andrey Miroshnikov authored
-
- 01 May, 2022 1 commit
-
-
Luke Kenneth Casson Leighton authored
blocks
-
- 30 Apr, 2022 4 commits
-
-
Luke Kenneth Casson Leighton authored
-
Luke Kenneth Casson Leighton authored
due to massive combinatorial chains
-
Luke Kenneth Casson Leighton authored
this is slightly complicated. the STATE regfile contains pc, msr, svstate, dec, and tb, being a reflection of CoreState. reading from STATE regfile is on a one-clock delay. the DEC/TB FSM needs to decrement DEC and increment TB, by reading from the STATE regfile and then writing a new value. of course, the SPR pipeline has to get a word in edgeways as well. but... the complication comes in that it is the PowerDecoder2 which receives a *cached* copy of DEC, and this cached copy is what has (up until now) been out-of-date with what is in the STATE regfile. the hack-job-solution is to zero-out the cached copy when the SPR pipeline writes a new value to DEC. the DEC/TB FSM will then rewrite a correct value into it. given that PowerDecoder2 only uses the MSB of DEC (and the EE bit of MSR) to determine whether to fire an interrupt, this should be perfectly fine.
-
Cesar Strauss authored
Add a bypass path when simultaneously reading and writing to the same address. There needs to be an independent Mux for each write lane, since we may not be writing on all lanes, necessarily.
-
- 29 Apr, 2022 5 commits
-
-
Jacob Lifshay authored
reduces 128x64->64-bit divider to 220k cells rather than 700k cells
-
Luke Kenneth Casson Leighton authored
issuer_verilog.py
-
Jacob Lifshay authored
-
Jacob Lifshay authored
-
Jacob Lifshay authored
-
- 28 Apr, 2022 7 commits
-
-
Cesar Strauss authored
Should catch some corner cases.
-
Jacob Lifshay authored
-
Jacob Lifshay authored
-
Luke Kenneth Casson Leighton authored
what dependencies the HDL has. dropping USD 16 million on 7nm Mask Charges you absolutely cannot have arbitrary software downloaded off the internet from external sources.
-
Jacob Lifshay authored
-
Jacob Lifshay authored
-
Jacob Lifshay authored
-
- 27 Apr, 2022 7 commits
-
-
Jacob Lifshay authored
-
Jacob Lifshay authored
-
Jacob Lifshay authored
-
Jacob Lifshay authored
-
Jacob Lifshay authored
-
Jacob Lifshay authored
-
Jacob Lifshay authored
-
- 26 Apr, 2022 2 commits
-
-
Jacob Lifshay authored
-
Jacob Lifshay authored
-
- 25 Apr, 2022 2 commits
-
-
Jacob Lifshay authored
-
Jacob Lifshay authored
-
- 23 Apr, 2022 1 commit
-
-
Jacob Lifshay authored
-