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Kestrel Collaboration
Kestrel LibreSoC
soc
Commits
52a661be
Commit
52a661be
authored
2 years ago
by
Raptor Engineering Development Team
Browse files
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Add LiteX compatibility mode
parent
1f2a29c0
Changes
5
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Inline
Side-by-side
Showing
5 changed files
with
73 additions
and
40 deletions
+73
-40
src/soc/experiment/dcache.py
src/soc/experiment/dcache.py
+5
-2
src/soc/experiment/icache.py
src/soc/experiment/icache.py
+4
-1
src/soc/minerva/wishbone.py
src/soc/minerva/wishbone.py
+4
-1
src/soc/simple/issuer.py
src/soc/simple/issuer.py
+53
-36
src/soc/simple/issuer_verilog.py
src/soc/simple/issuer_verilog.py
+7
-0
No files found.
src/soc/experiment/dcache.py
View file @
52a661be
...
...
@@ -747,6 +747,9 @@ class DCache(Elaboratable, DCacheConfig):
# test if microwatt compatibility is to be enabled
self
.
microwatt_compat
=
(
hasattr
(
pspec
,
"microwatt_compat"
)
and
(
pspec
.
microwatt_compat
==
True
))
# test if litex compatibility is to be enabled
self
.
litex_compat
=
(
hasattr
(
pspec
,
"litex_compat"
)
and
(
pspec
.
litex_compat
==
True
))
XLEN
=
pspec
.
XLEN
TLB_SET_SIZE
=
8
...
...
@@ -760,7 +763,7 @@ class DCache(Elaboratable, DCacheConfig):
TLB_NUM_WAYS
=
1
NUM_LINES
=
2
NUM_WAYS
=
1
if
self
.
microwatt_compat
:
if
self
.
microwatt_compat
or
self
.
litex_compat
:
# reduce way sizes
NUM_WAYS
=
1
TLB_NUM_WAYS
=
1
...
...
@@ -1855,7 +1858,7 @@ class DCache(Elaboratable, DCacheConfig):
# deal with litex not doing wishbone pipeline mode
# XXX in wrong way. FIFOs are needed in the SRAM test
# so that stb/ack match up. same thing done in icache.py
if
not
self
.
microwatt_compat
:
if
not
self
.
microwatt_compat
or
self
.
litex_compat
:
comb
+=
self
.
bus
.
stall
.
eq
(
self
.
bus
.
cyc
&
~
self
.
bus
.
ack
)
# Wire up wishbone request latch out of stage 1
...
...
This diff is collapsed.
Click to expand it.
src/soc/experiment/icache.py
View file @
52a661be
...
...
@@ -341,6 +341,9 @@ class ICache(FetchUnitInterface, Elaboratable, ICacheConfig):
# test if microwatt compatibility to be enabled
self
.
microwatt_compat
=
(
hasattr
(
pspec
,
"microwatt_compat"
)
and
(
pspec
.
microwatt_compat
==
True
))
# test if litex compatibility is to be enabled
self
.
litex_compat
=
(
hasattr
(
pspec
,
"litex_compat"
)
and
(
pspec
.
litex_compat
==
True
))
XLEN
=
pspec
.
XLEN
LINE_SIZE
=
64
...
...
@@ -352,7 +355,7 @@ class ICache(FetchUnitInterface, Elaboratable, ICacheConfig):
NUM_LINES
=
2
NUM_WAYS
=
1
TLB_SIZE
=
2
if
self
.
microwatt_compat
:
if
self
.
microwatt_compat
or
self
.
litex_compat
:
# reduce way sizes
NUM_WAYS
=
1
...
...
This diff is collapsed.
Click to expand it.
src/soc/minerva/wishbone.py
View file @
52a661be
...
...
@@ -21,6 +21,9 @@ def make_wb_layout(spec, cti=True):
# test if microwatt compatibility is to be enabled
microwatt_compat
=
(
hasattr
(
spec
,
"microwatt_compat"
)
and
(
spec
.
microwatt_compat
==
True
))
# test if litex compatibility is to be enabled
litex_compat
=
(
hasattr
(
spec
,
"litex_compat"
)
and
(
spec
.
litex_compat
==
True
))
res
=
[
(
"adr"
,
badwid
,
DIR_FANOUT
),
...
...
@@ -34,7 +37,7 @@ def make_wb_layout(spec, cti=True):
(
"err"
,
1
,
DIR_FANIN
)
]
# microwatt needs a stall signal (operates in pipeline mode)
if
microwatt_compat
:
if
microwatt_compat
or
litex_compat
:
res
.
append
((
"stall"
,
1
,
DIR_FANIN
))
if
not
cti
:
return
res
...
...
This diff is collapsed.
Click to expand it.
src/soc/simple/issuer.py
View file @
52a661be
...
...
@@ -169,8 +169,11 @@ class TestIssuerBase(Elaboratable):
self
.
microwatt_compat
=
(
hasattr
(
pspec
,
"microwatt_compat"
)
and
(
pspec
.
microwatt_compat
==
True
))
self
.
alt_reset
=
Signal
(
reset_less
=
True
)
# not connected yet (microwatt)
# test if litex compatibility is to be enabled
self
.
litex_compat
=
(
hasattr
(
pspec
,
"litex_compat"
)
and
(
pspec
.
litex_compat
==
True
))
if
self
.
microwatt_compat
:
if
self
.
microwatt_compat
or
self
.
litex_compat
:
if
hasattr
(
pspec
,
"microwatt_old"
):
self
.
microwatt_old
=
pspec
.
microwatt_old
...
...
@@ -335,13 +338,13 @@ class TestIssuerBase(Elaboratable):
# sigh, the wishbone addresses are not wishbone-compliant
# in old versions of microwatt, tplaten_3d_game is a new one
if
self
.
microwatt_compat
:
if
self
.
microwatt_compat
or
self
.
litex_compat
:
self
.
ibus_adr
=
Signal
(
32
,
name
=
'wishbone_insn_out.adr'
)
self
.
dbus_adr
=
Signal
(
32
,
name
=
'wishbone_data_out.adr'
)
# add an output of the PC and instruction, and whether it was requested
# this is for verilator debug purposes
if
self
.
microwatt_compat
:
if
self
.
microwatt_compat
or
self
.
litex_compat
:
self
.
nia
=
Signal
(
64
)
self
.
msr_o
=
Signal
(
64
)
self
.
nia_req
=
Signal
(
1
)
...
...
@@ -364,7 +367,7 @@ class TestIssuerBase(Elaboratable):
csd
=
DomainRenamer
(
self
.
core_domain
)
dbd
=
DomainRenamer
(
self
.
dbg_domain
)
if
self
.
microwatt_compat
:
if
self
.
microwatt_compat
or
self
.
litex_compat
:
m
.
submodules
.
core
=
core
=
self
.
core
else
:
m
.
submodules
.
core
=
core
=
csd
(
self
.
core
)
...
...
@@ -385,7 +388,7 @@ class TestIssuerBase(Elaboratable):
# fixup the clocks in microwatt-compat mode (but leave resets alone
# so that microwatt soc.vhdl can pull a reset on the core or DMI
# can do it, just like in TestIssuer)
if
self
.
microwatt_compat
:
if
self
.
microwatt_compat
or
self
.
litex_compat
:
intclk
=
ClockSignal
(
self
.
core_domain
)
dbgclk
=
ClockSignal
(
self
.
dbg_domain
)
if
self
.
core_domain
!=
'sync'
:
...
...
@@ -395,7 +398,7 @@ class TestIssuerBase(Elaboratable):
# if using old version of microwatt
# drop the first 3 bits of the incoming wishbone addresses
if
self
.
microwatt_compat
:
if
self
.
microwatt_compat
or
self
.
litex_compat
:
ibus
=
self
.
imem
.
ibus
dbus
=
self
.
core
.
l0
.
cmpi
.
wb_bus
()
if
self
.
microwatt_old
:
...
...
@@ -702,7 +705,7 @@ class TestIssuerBase(Elaboratable):
sync
+=
self
.
sv_changed
.
eq
(
1
)
# start renaming some of the ports to match microwatt
if
self
.
microwatt_compat
:
if
self
.
microwatt_compat
or
self
.
litex_compat
:
self
.
core
.
o
.
core_terminate_o
.
name
=
"terminated_out"
# names of DMI interface
self
.
dbg
.
dmi
.
addr_i
.
name
=
'dmi_addr'
...
...
@@ -713,26 +716,28 @@ class TestIssuerBase(Elaboratable):
self
.
dbg
.
dmi
.
ack_o
.
name
=
'dmi_ack'
# wishbone instruction bus
ibus
=
self
.
imem
.
ibus
ibus
.
adr
.
name
=
'wishbone_insn_out.adr'
ibus
.
dat_w
.
name
=
'wishbone_insn_out.dat'
ibus
.
sel
.
name
=
'wishbone_insn_out.sel'
ibus
.
cyc
.
name
=
'wishbone_insn_out.cyc'
ibus
.
stb
.
name
=
'wishbone_insn_out.stb'
ibus
.
we
.
name
=
'wishbone_insn_out.we'
ibus
.
dat_r
.
name
=
'wishbone_insn_in.dat'
ibus
.
ack
.
name
=
'wishbone_insn_in.ack'
ibus
.
stall
.
name
=
'wishbone_insn_in.stall'
if
self
.
microwatt_compat
:
ibus
.
adr
.
name
=
'wishbone_insn_out.adr'
ibus
.
dat_w
.
name
=
'wishbone_insn_out.dat'
ibus
.
sel
.
name
=
'wishbone_insn_out.sel'
ibus
.
cyc
.
name
=
'wishbone_insn_out.cyc'
ibus
.
stb
.
name
=
'wishbone_insn_out.stb'
ibus
.
we
.
name
=
'wishbone_insn_out.we'
ibus
.
dat_r
.
name
=
'wishbone_insn_in.dat'
ibus
.
ack
.
name
=
'wishbone_insn_in.ack'
ibus
.
stall
.
name
=
'wishbone_insn_in.stall'
# wishbone data bus
dbus
=
self
.
core
.
l0
.
cmpi
.
wb_bus
()
dbus
.
adr
.
name
=
'wishbone_data_out.adr'
dbus
.
dat_w
.
name
=
'wishbone_data_out.dat'
dbus
.
sel
.
name
=
'wishbone_data_out.sel'
dbus
.
cyc
.
name
=
'wishbone_data_out.cyc'
dbus
.
stb
.
name
=
'wishbone_data_out.stb'
dbus
.
we
.
name
=
'wishbone_data_out.we'
dbus
.
dat_r
.
name
=
'wishbone_data_in.dat'
dbus
.
ack
.
name
=
'wishbone_data_in.ack'
dbus
.
stall
.
name
=
'wishbone_data_in.stall'
if
self
.
microwatt_compat
:
dbus
.
adr
.
name
=
'wishbone_data_out.adr'
dbus
.
dat_w
.
name
=
'wishbone_data_out.dat'
dbus
.
sel
.
name
=
'wishbone_data_out.sel'
dbus
.
cyc
.
name
=
'wishbone_data_out.cyc'
dbus
.
stb
.
name
=
'wishbone_data_out.stb'
dbus
.
we
.
name
=
'wishbone_data_out.we'
dbus
.
dat_r
.
name
=
'wishbone_data_in.dat'
dbus
.
ack
.
name
=
'wishbone_data_in.ack'
dbus
.
stall
.
name
=
'wishbone_data_in.stall'
return
m
...
...
@@ -750,15 +755,24 @@ class TestIssuerBase(Elaboratable):
return
list
(
self
)
def
external_ports
(
self
):
if
self
.
microwatt_compat
:
ports
=
[
self
.
core
.
o
.
core_terminate_o
,
self
.
ext_irq
,
self
.
alt_reset
,
# not connected yet
self
.
nia
,
self
.
insn
,
self
.
nia_req
,
self
.
msr_o
,
self
.
ldst_req
,
self
.
ldst_addr
,
ClockSignal
(),
ResetSignal
(),
]
if
self
.
microwatt_compat
or
self
.
litex_compat
:
if
self
.
litex_compat
:
ports
=
[
self
.
core
.
o
.
core_terminate_o
,
self
.
alt_reset
,
# not connected yet
self
.
nia
,
self
.
insn
,
self
.
nia_req
,
self
.
msr_o
,
self
.
ldst_req
,
self
.
ldst_addr
,
ClockSignal
(),
ResetSignal
(),
]
else
:
ports
=
[
self
.
core
.
o
.
core_terminate_o
,
self
.
ext_irq
,
self
.
alt_reset
,
# not connected yet
self
.
nia
,
self
.
insn
,
self
.
nia_req
,
self
.
msr_o
,
self
.
ldst_req
,
self
.
ldst_addr
,
ClockSignal
(),
ResetSignal
(),
]
ports
+=
list
(
self
.
dbg
.
dmi
.
ports
())
# for dbus/ibus microwatt, exclude err btw and cti
for
name
,
sig
in
self
.
imem
.
ibus
.
fields
.
items
():
...
...
@@ -770,7 +784,10 @@ class TestIssuerBase(Elaboratable):
# microwatt non-compliant with wishbone
ports
.
append
(
self
.
ibus_adr
)
ports
.
append
(
self
.
dbus_adr
)
return
ports
if
self
.
microwatt_compat
:
# Ignore the remaining ports in microwatt compat mode
return
ports
ports
=
self
.
pc_i
.
ports
()
ports
=
self
.
msr_i
.
ports
()
...
...
@@ -925,7 +942,7 @@ class TestIssuerInternal(TestIssuerBase):
# not SVP64 - 32-bit only
sync
+=
nia
.
eq
(
cur_state
.
pc
+
4
)
sync
+=
dec_opcode_i
.
eq
(
insn
)
if
self
.
microwatt_compat
:
if
self
.
microwatt_compat
or
self
.
litex_compat
:
# for verilator debug purposes
comb
+=
self
.
insn
.
eq
(
insn
)
comb
+=
self
.
nia
.
eq
(
cur_state
.
pc
)
...
...
This diff is collapsed.
Click to expand it.
src/soc/simple/issuer_verilog.py
View file @
52a661be
...
...
@@ -77,6 +77,11 @@ if __name__ == '__main__':
action
=
"store_true"
,
help
=
"generate old microwatt-compatible interface"
,
default
=
False
)
# create a module with LiteX compatibility
parser
.
add_argument
(
"--litex-compat"
,
dest
=
'litexcompat'
,
action
=
"store_true"
,
help
=
"generate LiteX-compatible interface"
,
default
=
False
)
# small cache option
parser
.
add_argument
(
"--small-cache"
,
dest
=
'smallcache'
,
action
=
"store_true"
,
...
...
@@ -155,6 +160,7 @@ if __name__ == '__main__':
microwatt_compat
=
args
.
mwcompat
,
# microwatt compatible
microwatt_old
=
args
.
old_mwcompat
,
# old microwatt api
microwatt_debug
=
args
.
mwdebug
,
# microwatt debug signals
litex_compat
=
args
.
litexcompat
,
# litex compatible (overlaps with microwatt compat)
small_cache
=
args
.
smallcache
,
# small cache/TLB sizes
allow_overlap
=
args
.
allow_overlap
,
# allow overlap
units
=
units
,
...
...
@@ -178,6 +184,7 @@ if __name__ == '__main__':
print
(
"Microwatt compatibility"
,
pspec
.
__dict__
[
"microwatt_compat"
])
print
(
"Old Microwatt compatibility"
,
pspec
.
__dict__
[
"microwatt_old"
])
print
(
"Microwatt debug"
,
pspec
.
__dict__
[
"microwatt_debug"
])
print
(
"LiteX compatibility"
,
pspec
.
__dict__
[
"litex_compat"
])
print
(
"Small Cache/TLB"
,
pspec
.
__dict__
[
"small_cache"
])
if
args
.
mwcompat
:
...
...
This diff is collapsed.
Click to expand it.
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