Commit 7e837bf1 authored by Florent Kermarrec's avatar Florent Kermarrec
Browse files
parent 712977a0
......@@ -21,4 +21,4 @@
url = http://github.com/enjoy-digital/minerva-verilog
[submodule "litex/soc/cores/cpu/rocket/verilog"]
path = litex/soc/cores/cpu/rocket/verilog
url = https://github.com/gsomlo/rocket-litex-verilog
url = https://github.com/enjoy-digital/rocket-litex-verilog
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