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There is a conflict between the LiteX way of doing things and the POWER
way of handling interrupt tables.  LiteX expects to be able to put a ROM
at address 0 and load an application into RAM at a higher address; POWER
is architected to jump to exception handlers at 0x100...0x1000.

As a result of this, we have taken the approach of placing generic exception
handler entry / exit routines into ROM, and reserving a single pointer in
SRAM to determine the C ISR handler location.  If no application is loaded,
this pointer is set to the BIOS ROM ISR.  When an application loads, before
reenabling interrupts, it needs to set __rom_isr_address to the address of
the application's ISR, otherwise the BIOS ROM ISR will continue to be used.

Tested to operate with the built-in UART in IRQ mode, both in BIOS and in
loaded RAM application.