- 22 Jan, 2020 3 commits
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
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- 21 Jan, 2020 1 commit
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Florent Kermarrec authored
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- 18 Jan, 2020 3 commits
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
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- 17 Jan, 2020 2 commits
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Florent Kermarrec authored
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Florent Kermarrec authored
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- 16 Jan, 2020 6 commits
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Tim 'mithro' Ansell authored
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Florent Kermarrec authored
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Florent Kermarrec authored
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enjoy-digital authored
Add Mimas A7 board support
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Florent Kermarrec authored
aller/tagus/nereid: use crossover UART, rename SoC to PCIe SoC and pass soc_sdram_argdict to PCIeSoC
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Florent Kermarrec authored
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- 15 Jan, 2020 3 commits
- 13 Jan, 2020 6 commits
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Florent Kermarrec authored
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Florent Kermarrec authored
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enjoy-digital authored
ADD: KX2 and DDR3 support
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Florent Kermarrec authored
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Florent Kermarrec authored
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Mark authored
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- 11 Jan, 2020 1 commit
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Florent Kermarrec authored
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- 10 Jan, 2020 2 commits
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Florent Kermarrec authored
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Florent Kermarrec authored
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- 09 Jan, 2020 8 commits
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
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enjoy-digital authored
targets/de10lite: use external clock for sys directly
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Marcin Sloniewski authored
At the start output of the pll is not stabilized, which caused malfunctions when used for sys clock domain. Use AsyncResetSynchronizer to start clock domains on pll locked signal.
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Gabriel Somlo authored
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Florent Kermarrec authored
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- 08 Jan, 2020 2 commits
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Florent Kermarrec authored
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Florent Kermarrec authored
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- 07 Jan, 2020 3 commits
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Florent Kermarrec authored
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Florent Kermarrec authored
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enjoy-digital authored
add the Hackaday Supercon ECP5 badge
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