Skip to content
GitLab
Projects
Groups
Snippets
Help
Loading...
Help
Help
Support
Community forum
Keyboard shortcuts
?
Submit feedback
Contribute to GitLab
Sign in / Register
Toggle navigation
Open sidebar
Timothy Pearson
litex-boards
Commits
d87a11a9
Commit
d87a11a9
authored
4 years ago
by
Florent Kermarrec
Browse files
Options
Download
Email Patches
Plain Diff
targets/pcie: use generate_litepcie_software on all targets with PCIe.
parent
9f83b6e3
Changes
3
Hide whitespace changes
Inline
Side-by-side
Showing
3 changed files
with
24 additions
and
47 deletions
+24
-47
litex_boards/targets/aller.py
litex_boards/targets/aller.py
+8
-15
litex_boards/targets/nereid.py
litex_boards/targets/nereid.py
+8
-17
litex_boards/targets/tagus.py
litex_boards/targets/tagus.py
+8
-15
No files found.
litex_boards/targets/aller.py
View file @
d87a11a9
...
...
@@ -11,15 +11,12 @@ import sys
from
migen
import
*
from
migen.genlib.misc
import
WaitTimer
from
litex.build
import
tools
from
litex_boards.platforms
import
aller
from
litex.soc.interconnect.csr
import
*
from
litex.soc.integration.soc_core
import
*
from
litex.soc.integration.soc_sdram
import
*
from
litex.soc.integration.builder
import
*
from
litex.soc.integration.export
import
*
from
litex.soc.cores.clock
import
*
from
litex.soc.cores.dna
import
DNA
...
...
@@ -34,6 +31,7 @@ from litepcie.phy.s7pciephy import S7PCIEPHY
from
litepcie.core
import
LitePCIeEndpoint
,
LitePCIeMSI
from
litepcie.frontend.dma
import
LitePCIeDMA
from
litepcie.frontend.wishbone
import
LitePCIeWishboneBridge
from
litepcie.software
import
generate_litepcie_software
# CRG ----------------------------------------------------------------------------------------------
...
...
@@ -164,20 +162,13 @@ class PCIeSoC(SoCCore):
sys_clk_freq
=
sys_clk_freq
)
self
.
add_csr
(
"leds"
)
def
generate_software_headers
(
self
):
csr_header
=
get_csr_header
(
self
.
csr_regions
,
self
.
constants
,
with_access_functions
=
False
)
tools
.
write_to_file
(
"csr.h"
,
csr_header
)
soc_header
=
get_soc_header
(
self
.
constants
,
with_access_functions
=
False
)
tools
.
write_to_file
(
"soc.h"
,
soc_header
)
mem_header
=
get_mem_header
(
self
.
mem_regions
)
tools
.
write_to_file
(
"mem.h"
,
mem_header
)
# Build --------------------------------------------------------------------------------------------
def
main
():
parser
=
argparse
.
ArgumentParser
(
description
=
"LiteX SoC on Aller"
)
parser
.
add_argument
(
"--build"
,
action
=
"store_true"
,
help
=
"Build bitstream"
)
parser
.
add_argument
(
"--load"
,
action
=
"store_true"
,
help
=
"Load bitstream"
)
parser
.
add_argument
(
"--build"
,
action
=
"store_true"
,
help
=
"Build bitstream"
)
parser
.
add_argument
(
"--driver"
,
action
=
"store_true"
,
help
=
"Generate LitePCIe driver"
)
parser
.
add_argument
(
"--load"
,
action
=
"store_true"
,
help
=
"Load bitstream"
)
builder_args
(
parser
)
soc_sdram_args
(
parser
)
args
=
parser
.
parse_args
()
...
...
@@ -189,8 +180,10 @@ def main():
platform
=
aller
.
Platform
()
soc
=
PCIeSoC
(
platform
,
**
soc_sdram_argdict
(
args
))
builder
=
Builder
(
soc
,
**
builder_argdict
(
args
))
vns
=
builder
.
build
(
run
=
args
.
build
)
soc
.
generate_software_headers
()
builder
.
build
(
run
=
args
.
build
)
if
args
.
driver
:
generate_litepcie_software
(
soc
,
os
.
path
.
join
(
builder
.
output_dir
,
"driver"
))
if
args
.
load
:
prog
=
soc
.
platform
.
create_programmer
()
...
...
This diff is collapsed.
Click to expand it.
litex_boards/targets/nereid.py
View file @
d87a11a9
...
...
@@ -11,15 +11,12 @@ import sys
from
migen
import
*
from
migen.genlib.misc
import
WaitTimer
from
litex.build
import
tools
from
litex_boards.platforms
import
nereid
from
litex.soc.interconnect.csr
import
*
from
litex.soc.integration.soc_core
import
*
from
litex.soc.integration.soc_sdram
import
*
from
litex.soc.integration.builder
import
*
from
litex.soc.integration.export
import
*
from
litex.soc.cores.clock
import
*
from
litex.soc.cores.dna
import
DNA
...
...
@@ -33,8 +30,7 @@ from litepcie.phy.s7pciephy import S7PCIEPHY
from
litepcie.core
import
LitePCIeEndpoint
,
LitePCIeMSI
from
litepcie.frontend.dma
import
LitePCIeDMA
from
litepcie.frontend.wishbone
import
LitePCIeWishboneBridge
from
litepcie.software
import
generate_litepcie_software
# CRG ----------------------------------------------------------------------------------------------
...
...
@@ -157,20 +153,13 @@ class PCIeSoC(SoCCore):
self
.
comb
+=
self
.
pcie_msi
.
irqs
[
i
].
eq
(
v
)
self
.
add_constant
(
k
+
"_INTERRUPT"
,
i
)
def
generate_software_headers
(
self
):
csr_header
=
get_csr_header
(
self
.
csr_regions
,
self
.
constants
,
with_access_functions
=
False
)
tools
.
write_to_file
(
"csr.h"
,
csr_header
)
soc_header
=
get_soc_header
(
self
.
constants
,
with_access_functions
=
False
)
tools
.
write_to_file
(
"soc.h"
,
soc_header
)
mem_header
=
get_mem_header
(
self
.
mem_regions
)
tools
.
write_to_file
(
"mem.h"
,
mem_header
)
# Build --------------------------------------------------------------------------------------------
def
main
():
parser
=
argparse
.
ArgumentParser
(
description
=
"LiteX SoC on Nereid"
)
parser
.
add_argument
(
"--build"
,
action
=
"store_true"
,
help
=
"Build bitstream"
)
parser
.
add_argument
(
"--load"
,
action
=
"store_true"
,
help
=
"Load bitstream"
)
parser
.
add_argument
(
"--build"
,
action
=
"store_true"
,
help
=
"Build bitstream"
)
parser
.
add_argument
(
"--driver"
,
action
=
"store_true"
,
help
=
"Generate LitePCIe driver"
)
parser
.
add_argument
(
"--load"
,
action
=
"store_true"
,
help
=
"Load bitstream"
)
builder_args
(
parser
)
soc_sdram_args
(
parser
)
args
=
parser
.
parse_args
()
...
...
@@ -182,8 +171,10 @@ def main():
platform
=
nereid
.
Platform
()
soc
=
PCIeSoC
(
platform
,
**
soc_sdram_argdict
(
args
))
builder
=
Builder
(
soc
,
**
builder_argdict
(
args
))
vns
=
builder
.
build
(
run
=
args
.
build
)
soc
.
generate_software_headers
()
builder
.
build
(
run
=
args
.
build
)
if
args
.
driver
:
generate_litepcie_software
(
soc
,
os
.
path
.
join
(
builder
.
output_dir
,
"driver"
))
if
args
.
load
:
prog
=
soc
.
platform
.
create_programmer
()
...
...
This diff is collapsed.
Click to expand it.
litex_boards/targets/tagus.py
View file @
d87a11a9
...
...
@@ -11,15 +11,12 @@ import sys
from
migen
import
*
from
migen.genlib.misc
import
WaitTimer
from
litex.build
import
tools
from
litex_boards.platforms
import
tagus
from
litex.soc.interconnect.csr
import
*
from
litex.soc.integration.soc_core
import
*
from
litex.soc.integration.soc_sdram
import
*
from
litex.soc.integration.builder
import
*
from
litex.soc.integration.export
import
*
from
litex.soc.cores.clock
import
*
from
litex.soc.cores.dna
import
DNA
...
...
@@ -34,6 +31,7 @@ from litepcie.phy.s7pciephy import S7PCIEPHY
from
litepcie.core
import
LitePCIeEndpoint
,
LitePCIeMSI
from
litepcie.frontend.dma
import
LitePCIeDMA
from
litepcie.frontend.wishbone
import
LitePCIeWishboneBridge
from
litepcie.software
import
generate_litepcie_software
# CRG ----------------------------------------------------------------------------------------------
...
...
@@ -164,20 +162,13 @@ class PCIeSoC(SoCCore):
sys_clk_freq
=
sys_clk_freq
)
self
.
add_csr
(
"leds"
)
def
generate_software_headers
(
self
):
csr_header
=
get_csr_header
(
self
.
csr_regions
,
self
.
constants
,
with_access_functions
=
False
)
tools
.
write_to_file
(
"csr.h"
,
csr_header
)
soc_header
=
get_soc_header
(
self
.
constants
,
with_access_functions
=
False
)
tools
.
write_to_file
(
"soc.h"
,
soc_header
)
mem_header
=
get_mem_header
(
self
.
mem_regions
)
tools
.
write_to_file
(
"mem.h"
,
mem_header
)
# Build --------------------------------------------------------------------------------------------
def
main
():
parser
=
argparse
.
ArgumentParser
(
description
=
"LiteX SoC on Tagus"
)
parser
.
add_argument
(
"--build"
,
action
=
"store_true"
,
help
=
"Build bitstream"
)
parser
.
add_argument
(
"--load"
,
action
=
"store_true"
,
help
=
"Load bitstream"
)
parser
.
add_argument
(
"--build"
,
action
=
"store_true"
,
help
=
"Build bitstream"
)
parser
.
add_argument
(
"--driver"
,
action
=
"store_true"
,
help
=
"Generate LitePCIe driver"
)
parser
.
add_argument
(
"--load"
,
action
=
"store_true"
,
help
=
"Load bitstream"
)
builder_args
(
parser
)
soc_sdram_args
(
parser
)
args
=
parser
.
parse_args
()
...
...
@@ -189,8 +180,10 @@ def main():
platform
=
tagus
.
Platform
()
soc
=
PCIeSoC
(
platform
,
**
soc_sdram_argdict
(
args
))
builder
=
Builder
(
soc
,
**
builder_argdict
(
args
))
vns
=
builder
.
build
(
run
=
args
.
build
)
soc
.
generate_software_headers
()
builder
.
build
(
run
=
args
.
build
)
if
args
.
driver
:
generate_litepcie_software
(
soc
,
os
.
path
.
join
(
builder
.
output_dir
,
"driver"
))
if
args
.
load
:
prog
=
soc
.
platform
.
create_programmer
()
...
...
This diff is collapsed.
Click to expand it.
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
.
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment