Commit c94cbae0 authored by Florent Kermarrec's avatar Florent Kermarrec
Browse files

orangecrab: add user_led (RGB leds), DFUProg and --load support.

parent 9aea2272
......@@ -3,6 +3,7 @@
from litex.build.generic_platform import *
from litex.build.lattice import LatticePlatform
from litex.build.dfu import DFUProg
# IOs ----------------------------------------------------------------------------------------------
......@@ -15,6 +16,10 @@ _io_r0_1 = [
Subsignal("b", Pins("J3"), IOStandard("LVCMOS33")),
),
("user_led", 0, Pins("V17"), IOStandard("LVCMOS33")), # rgb_led.r
("user_led", 1, Pins("V17"), IOStandard("LVCMOS33")), # rgb_led.g
("user_led", 2, Pins("V17"), IOStandard("LVCMOS33")), # rgb_led.b
("ddram", 0,
Subsignal("a", Pins(
"A4 D2 C3 C7 D3 D4 D1 B2",
......@@ -78,6 +83,10 @@ _io_r0_2 = [
Subsignal("b", Pins("J3"), IOStandard("LVCMOS33")),
),
("user_led", 0, Pins("K4"), IOStandard("LVCMOS33")), # rgb_led.r
("user_led", 1, Pins("M3"), IOStandard("LVCMOS33")), # rgb_led.g
("user_led", 2, Pins("J3"), IOStandard("LVCMOS33")), # rgb_led.b
("ddram", 0,
Subsignal("a", Pins(
"C4 D2 D3 A3 A4 D4 C3 B2",
......@@ -189,6 +198,9 @@ class Platform(LatticePlatform):
connectors = {"0.1": _connectors_r0_1, "0.2": _connectors_r0_2}[revision]
LatticePlatform.__init__(self, f"LFE5U-{device}-8MG285C", io, connectors, **kwargs)
def create_programmer(self):
return DFUProg(vid="1209", pid="5bf0")
def do_finalize(self, fragment):
LatticePlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk48", loose=True), 1e9/48e6)
......@@ -17,6 +17,7 @@ from litex.soc.cores.clock import *
from litex.soc.integration.soc_core import *
from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import *
from litex.soc.cores.led import LedChaser
from litedram.modules import MT41K64M16, MT41K128M16, MT41K256M16, MT41K512M16
from litedram.phy import ECP5DDRPHY
......@@ -105,7 +106,7 @@ class BaseSoC(SoCCore):
"MT41K64M16": MT41K64M16,
"MT41K128M16": MT41K128M16,
"MT41K256M16": MT41K256M16,
"MT41K512M16": MT41K512M16
"MT41K512M16": MT41K512M16,
}
sdram_module = available_sdram_modules.get(sdram_device)
......@@ -124,11 +125,18 @@ class BaseSoC(SoCCore):
l2_cache_reverse = True
)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
pads = Cat(*[platform.request("user_led", i) for i in range(3)]),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
# Build --------------------------------------------------------------------------------------------
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on OrangeCrab")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond")
builder_args(parser)
soc_sdram_args(parser)
......@@ -139,15 +147,20 @@ def main():
parser.add_argument("--sdram-device", default="MT41K64M16", help="ECP5 device (default=MT41K64M16)")
args = parser.parse_args()
soc = BaseSoC(toolchain=args.toolchain,
revision=args.revision,
device=args.device,
sdram_device=args.sdram_device,
sys_clk_freq=int(float(args.sys_clk_freq)),
**soc_sdram_argdict(args))
soc = BaseSoC(
toolchain = args.toolchain,
revision = args.revision,
device = args.device,
sdram_device = args.sdram_device,
sys_clk_freq = int(float(args.sys_clk_freq)),
**soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {}
builder.build(**builder_kargs, run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
if __name__ == "__main__":
main()
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