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Timothy Pearson
litex-boards
Commits
a7d6de78
Commit
a7d6de78
authored
4 years ago
by
Vamsi K Vytla
Browse files
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Merge branch 'master' into marblemini
parents
5f7f087c
19b12fd9
Changes
115
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20 changed files
with
717 additions
and
361 deletions
+717
-361
.travis.yml
.travis.yml
+7
-3
README
README
+1
-13
litex_boards/community/targets/__init__.py
litex_boards/community/targets/__init__.py
+0
-0
litex_boards/official/__init__.py
litex_boards/official/__init__.py
+0
-0
litex_boards/official/platforms/__init__.py
litex_boards/official/platforms/__init__.py
+0
-0
litex_boards/official/platforms/versa_ecp3.py
litex_boards/official/platforms/versa_ecp3.py
+0
-136
litex_boards/official/targets/__init__.py
litex_boards/official/targets/__init__.py
+0
-0
litex_boards/partner/__init__.py
litex_boards/partner/__init__.py
+0
-0
litex_boards/partner/platforms/__init__.py
litex_boards/partner/platforms/__init__.py
+0
-0
litex_boards/partner/platforms/orangecrab.py
litex_boards/partner/platforms/orangecrab.py
+0
-62
litex_boards/partner/targets/__init__.py
litex_boards/partner/targets/__init__.py
+0
-0
litex_boards/platforms.py
litex_boards/platforms.py
+0
-15
litex_boards/platforms/__init__.py
litex_boards/platforms/__init__.py
+0
-0
litex_boards/platforms/ac701.py
litex_boards/platforms/ac701.py
+232
-0
litex_boards/platforms/acorn_cle_215.py
litex_boards/platforms/acorn_cle_215.py
+100
-0
litex_boards/platforms/aller.py
litex_boards/platforms/aller.py
+40
-34
litex_boards/platforms/arty.py
litex_boards/platforms/arty.py
+63
-53
litex_boards/platforms/arty_s7.py
litex_boards/platforms/arty_s7.py
+219
-0
litex_boards/platforms/avalanche.py
litex_boards/platforms/avalanche.py
+22
-17
litex_boards/platforms/c10lprefkit.py
litex_boards/platforms/c10lprefkit.py
+33
-28
No files found.
.travis.yml
View file @
a7d6de78
...
@@ -4,10 +4,12 @@ python: "3.6"
...
@@ -4,10 +4,12 @@ python: "3.6"
install
:
install
:
# Get Migen / LiteX / Cores
# Get Migen / LiteX / Cores
-
cd ~/
-
wget https://raw.githubusercontent.com/enjoy-digital/litex/master/litex_setup.py
-
wget https://raw.githubusercontent.com/enjoy-digital/litex/master/litex_setup.py
-
python3 litex_setup.py init install
-
python3 litex_setup.py init install
# Install LiteX-Boards
# Install the version being tested
-
python3 setup.py develop
-
cd $TRAVIS_BUILD_DIR
-
python3 setup.py install
before_script
:
before_script
:
# Get RISC-V toolchain
# Get RISC-V toolchain
...
@@ -15,4 +17,6 @@ before_script:
...
@@ -15,4 +17,6 @@ before_script:
-
tar -xvf riscv64-unknown-elf-gcc-8.1.0-2019.01.0-x86_64-linux-ubuntu14.tar.gz
-
tar -xvf riscv64-unknown-elf-gcc-8.1.0-2019.01.0-x86_64-linux-ubuntu14.tar.gz
-
export PATH=$PATH:$PWD/riscv64-unknown-elf-gcc-8.1.0-2019.01.0-x86_64-linux-ubuntu14/bin/
-
export PATH=$PATH:$PWD/riscv64-unknown-elf-gcc-8.1.0-2019.01.0-x86_64-linux-ubuntu14/bin/
script
:
python setup.py test
script
:
-
cd $TRAVIS_BUILD_DIR
-
python setup.py test
This diff is collapsed.
Click to expand it.
README
View file @
a7d6de78
...
@@ -5,20 +5,8 @@
...
@@ -5,20 +5,8 @@
LiteX boards files
LiteX boards files
Copyright 2012-20
19
/ LiteX-Hub community
Copyright 2012-20
20
/ LiteX-Hub community
[> Intro
[> Intro
--------
--------
Supported boards files (platforms/targets) for LiteX.
Supported boards files (platforms/targets) for LiteX.
Official:
---------
Platforms / Targets actively tested and included in the CI system.
Partner:
-------
Platforms / Targets supported by other groups/partners.
Community:
----------
Platforms / Targets supported by the community in a "best effort" manner.
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litex_boards/community/targets/__init__.py
deleted
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5f7f087c
This diff is collapsed.
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litex_boards/official/__init__.py
deleted
100644 → 0
View file @
5f7f087c
This diff is collapsed.
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litex_boards/official/platforms/__init__.py
deleted
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5f7f087c
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litex_boards/official/platforms/versa_ecp3.py
deleted
100644 → 0
View file @
5f7f087c
# This file is Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr>
# License: BSD
from
litex.build.generic_platform
import
*
from
litex.build.lattice
import
LatticePlatform
from
litex.build.lattice.programmer
import
LatticeProgrammer
# IOs ----------------------------------------------------------------------------------------------
_io
=
[
(
"clk100"
,
0
,
Pins
(
"L5"
),
IOStandard
(
"LVDS25"
)),
(
"rst_n"
,
0
,
Pins
(
"A21"
),
IOStandard
(
"LVCMOS33"
)),
(
"user_led"
,
0
,
Pins
(
"Y20"
),
IOStandard
(
"LVCMOS33"
)),
(
"user_led"
,
1
,
Pins
(
"AA21"
),
IOStandard
(
"LVCMOS33"
)),
(
"user_led"
,
2
,
Pins
(
"U18"
),
IOStandard
(
"LVCMOS33"
)),
(
"user_led"
,
3
,
Pins
(
"U19"
),
IOStandard
(
"LVCMOS33"
)),
(
"user_led"
,
4
,
Pins
(
"W19"
),
IOStandard
(
"LVCMOS33"
)),
(
"user_led"
,
5
,
Pins
(
"V19"
),
IOStandard
(
"LVCMOS33"
)),
(
"user_led"
,
6
,
Pins
(
"AB20"
),
IOStandard
(
"LVCMOS33"
)),
(
"user_led"
,
7
,
Pins
(
"AA20"
),
IOStandard
(
"LVCMOS33"
)),
(
"user_dip_btn"
,
0
,
Pins
(
"J7"
),
IOStandard
(
"LVCMOS15"
)),
(
"user_dip_btn"
,
1
,
Pins
(
"J6"
),
IOStandard
(
"LVCMOS15"
)),
(
"user_dip_btn"
,
2
,
Pins
(
"H2"
),
IOStandard
(
"LVCMOS15"
)),
(
"user_dip_btn"
,
3
,
Pins
(
"H3"
),
IOStandard
(
"LVCMOS15"
)),
(
"user_dip_btn"
,
4
,
Pins
(
"J3"
),
IOStandard
(
"LVCMOS15"
)),
(
"user_dip_btn"
,
5
,
Pins
(
"K3"
),
IOStandard
(
"LVCMOS15"
)),
(
"user_dip_btn"
,
6
,
Pins
(
"J2"
),
IOStandard
(
"LVCMOS15"
)),
(
"user_dip_btn"
,
7
,
Pins
(
"J1"
),
IOStandard
(
"LVCMOS15"
)),
(
"serial"
,
0
,
Subsignal
(
"tx"
,
Pins
(
"B11"
),
IOStandard
(
"LVCMOS33"
)),
# X4 IO0
Subsignal
(
"rx"
,
Pins
(
"B12"
),
IOStandard
(
"LVCMOS33"
)),
# X4 IO1
),
(
"eth_clocks"
,
0
,
Subsignal
(
"tx"
,
Pins
(
"C12"
)),
Subsignal
(
"gtx"
,
Pins
(
"M2"
)),
Subsignal
(
"rx"
,
Pins
(
"L4"
)),
IOStandard
(
"LVCMOS33"
)
),
(
"eth"
,
0
,
Subsignal
(
"rst_n"
,
Pins
(
"L3"
)),
Subsignal
(
"mdio"
,
Pins
(
"L2"
)),
Subsignal
(
"mdc"
,
Pins
(
"V4"
)),
Subsignal
(
"dv"
,
Pins
(
"M1"
)),
Subsignal
(
"rx_er"
,
Pins
(
"M4"
)),
Subsignal
(
"rx_data"
,
Pins
(
"M5 N1 N6 P6 T2 R2 P5 P3"
)),
Subsignal
(
"tx_en"
,
Pins
(
"V3"
)),
Subsignal
(
"tx_data"
,
Pins
(
"V1 U1 R3 P1 N5 N3 N4 N2"
)),
Subsignal
(
"col"
,
Pins
(
"R1"
)),
Subsignal
(
"crs"
,
Pins
(
"P4"
)),
IOStandard
(
"LVCMOS33"
)
),
(
"eth_clocks"
,
1
,
Subsignal
(
"tx"
,
Pins
(
"M21"
)),
Subsignal
(
"gtx"
,
Pins
(
"M19"
)),
Subsignal
(
"rx"
,
Pins
(
"N19"
)),
IOStandard
(
"LVCMOS33"
)
),
(
"eth"
,
1
,
Subsignal
(
"rst_n"
,
Pins
(
"R21"
)),
Subsignal
(
"mdio"
,
Pins
(
"U16"
)),
Subsignal
(
"mdc"
,
Pins
(
"Y18"
)),
Subsignal
(
"dv"
,
Pins
(
"U15"
)),
Subsignal
(
"rx_er"
,
Pins
(
"V20"
)),
Subsignal
(
"rx_data"
,
Pins
(
"AB17 AA17 R19 V21 T17 R18 W21 Y21"
)),
Subsignal
(
"tx_en"
,
Pins
(
"V22"
)),
Subsignal
(
"tx_data"
,
Pins
(
"W22 R16 P17 Y22 T21 U22 P20 U20"
)),
Subsignal
(
"col"
,
Pins
(
"N18"
)),
Subsignal
(
"crs"
,
Pins
(
"P19"
)),
IOStandard
(
"LVCMOS33"
)
),
]
# Platform -----------------------------------------------------------------------------------------
class
Platform
(
LatticePlatform
):
default_clk_name
=
"clk100"
default_clk_period
=
1e9
/
100e6
def
__init__
(
self
):
LatticePlatform
.
__init__
(
self
,
"LFE3-35EA-6FN484C"
,
_io
)
def
do_finalize
(
self
,
fragment
):
LatticePlatform
.
do_finalize
(
self
,
fragment
)
try
:
self
.
add_period_constraint
(
self
.
lookup_request
(
"eth_clocks"
,
0
).
rx
,
1e9
/
125e6
)
except
ConstraintError
:
pass
try
:
self
.
add_period_constraint
(
self
.
lookup_request
(
"eth_clocks"
,
1
).
rx
,
1e9
/
125e6
)
except
ConstraintError
:
pass
def
create_programmer
(
self
):
_xcf_template
=
"""
<?xml version='1.0' encoding='utf-8' ?>
<!DOCTYPE ispXCF SYSTEM "IspXCF.dtd" >
<ispXCF version="3.4.1">
<Comment></Comment>
<Chain>
<Comm>JTAG</Comm>
<Device>
<SelectedProg value="TRUE"/>
<Pos>1</Pos>
<Vendor>Lattice</Vendor>
<Family>LatticeECP3</Family>
<Name>LFE3-35EA</Name>
<File>{bitstream_file}</File>
<Operation>Fast Program</Operation>
</Device>
</Chain>
<ProjectOptions>
<Program>SEQUENTIAL</Program>
<Process>ENTIRED CHAIN</Process>
<OperationOverride>No Override</OperationOverride>
<StartTAP>TLR</StartTAP>
<EndTAP>TLR</EndTAP>
<VerifyUsercode value="FALSE"/>
</ProjectOptions>
<CableOptions>
<CableName>USB2</CableName>
<PortAdd>FTUSB-0</PortAdd>
<USBID>Dual RS232-HS A Location 0000 Serial A</USBID>
<JTAGPinSetting>
TRST ABSENT;
ISPEN ABSENT;
</JTAGPinSetting>
</CableOptions>
</ispXCF>
"""
return
LatticeProgrammer
(
_xcf_template
)
This diff is collapsed.
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litex_boards/official/targets/__init__.py
deleted
100644 → 0
View file @
5f7f087c
This diff is collapsed.
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litex_boards/partner/__init__.py
deleted
100644 → 0
View file @
5f7f087c
This diff is collapsed.
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litex_boards/partner/platforms/__init__.py
deleted
100644 → 0
View file @
5f7f087c
This diff is collapsed.
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litex_boards/partner/platforms/orangecrab.py
deleted
100644 → 0
View file @
5f7f087c
# This file is Copyright (c) 2019 Greg Davill <greg.davill@gmail.com>
# License: BSD
from
litex.build.generic_platform
import
*
from
litex.build.lattice
import
LatticePlatform
# IOs ----------------------------------------------------------------------------------------------
_io
=
[
(
"clk48"
,
0
,
Pins
(
"A9"
),
IOStandard
(
"LVCMOS33"
)),
(
"rgb_led"
,
0
,
Subsignal
(
"r"
,
Pins
(
"V17"
),
IOStandard
(
"LVCMOS25"
)),
Subsignal
(
"g"
,
Pins
(
"T17"
),
IOStandard
(
"LVCMOS25"
)),
Subsignal
(
"b"
,
Pins
(
"J3"
),
IOStandard
(
"LVCMOS33"
)),
),
(
"serial"
,
0
,
Subsignal
(
"tx"
,
Pins
(
"N17"
),
IOStandard
(
"LVCMOS25"
)),
Subsignal
(
"rx"
,
Pins
(
"M18"
),
IOStandard
(
"LVCMOS25"
)),
),
(
"ddram"
,
0
,
Subsignal
(
"a"
,
Pins
(
"A4 D2 C3 C7 D3 D4 D1 B2"
,
"C1 A2 A7 C2 C4"
),
IOStandard
(
"SSTL135_I"
)),
Subsignal
(
"ba"
,
Pins
(
"B6 B7 A6"
),
IOStandard
(
"SSTL135_I"
)),
Subsignal
(
"ras_n"
,
Pins
(
"C12"
),
IOStandard
(
"SSTL135_I"
)),
Subsignal
(
"cas_n"
,
Pins
(
"D13"
),
IOStandard
(
"SSTL135_I"
)),
Subsignal
(
"we_n"
,
Pins
(
"B12"
),
IOStandard
(
"SSTL135_I"
)),
Subsignal
(
"cs_n"
,
Pins
(
"A12"
),
IOStandard
(
"SSTL135_I"
)),
Subsignal
(
"dm"
,
Pins
(
"D16 G16"
),
IOStandard
(
"SSTL135_I"
)),
Subsignal
(
"dq"
,
Pins
(
"C17 D15 B17 C16 A15 B13 A17 A13"
,
"F17 F16 G15 F15 J16 C18 H16 F18"
),
IOStandard
(
"SSTL135_I"
),
Misc
(
"TERMINATION=75"
)),
Subsignal
(
"dqs_p"
,
Pins
(
"B15 G18"
),
IOStandard
(
"SSTL135D_I"
),
Misc
(
"TERMINATION=OFF DIFFRESISTOR=100"
)),
Subsignal
(
"clk_p"
,
Pins
(
"J18"
),
IOStandard
(
"SSTL135D_I"
)),
Subsignal
(
"cke"
,
Pins
(
"D6"
),
IOStandard
(
"SSTL135_I"
)),
Subsignal
(
"odt"
,
Pins
(
"C13"
),
IOStandard
(
"SSTL135_I"
)),
Subsignal
(
"reset_n"
,
Pins
(
"B1"
),
IOStandard
(
"SSTL135_I"
)),
Misc
(
"SLEWRATE=FAST"
)
),
(
"spiflash4x"
,
0
,
Subsignal
(
"cs_n"
,
Pins
(
"U17"
)),
Subsignal
(
"clk"
,
Pins
(
"U16"
)),
Subsignal
(
"dq"
,
Pins
(
"U18"
,
"T18"
,
"R18"
,
"N18"
)),
IOStandard
(
"LVCMOS25"
)
),
]
# Platform -----------------------------------------------------------------------------------------
class
Platform
(
LatticePlatform
):
default_clk_name
=
"clk48"
default_clk_period
=
1e9
/
48e6
def
__init__
(
self
,
**
kwargs
):
LatticePlatform
.
__init__
(
self
,
"LFE5U-25F-8MG285C"
,
_io
,
**
kwargs
)
This diff is collapsed.
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litex_boards/partner/targets/__init__.py
deleted
100644 → 0
View file @
5f7f087c
This diff is collapsed.
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litex_boards/platforms.py
deleted
100644 → 0
View file @
5f7f087c
import
sys
import
importlib
class
Platforms
:
def
__getattr__
(
self
,
name
):
if
name
==
"__path__"
:
return
[]
for
support
in
[
"official"
,
"partner"
,
"community"
]:
try
:
return
importlib
.
import_module
(
"litex_boards."
+
support
+
".platforms."
+
name
)
except
ModuleNotFoundError
:
pass
raise
ModuleNotFoundError
sys
.
modules
[
__name__
]
=
Platforms
()
This diff is collapsed.
Click to expand it.
litex_boards/
community
/__init__.py
→
litex_boards/
platforms
/__init__.py
View file @
a7d6de78
File moved
This diff is collapsed.
Click to expand it.
litex_boards/
community/
platforms/ac701.py
→
litex_boards/platforms/ac701.py
View file @
a7d6de78
...
@@ -2,7 +2,8 @@
...
@@ -2,7 +2,8 @@
# License: BSD
# License: BSD
from
litex.build.generic_platform
import
*
from
litex.build.generic_platform
import
*
from
litex.build.xilinx
import
XilinxPlatform
,
VivadoProgrammer
from
litex.build.xilinx
import
XilinxPlatform
from
litex.build.openocd
import
OpenOCD
# IOs ----------------------------------------------------------------------------------------------
# IOs ----------------------------------------------------------------------------------------------
...
@@ -27,8 +28,8 @@ _io = [
...
@@ -27,8 +28,8 @@ _io = [
(
"serial"
,
0
,
(
"serial"
,
0
,
Subsignal
(
"cts"
,
Pins
(
"V19"
)),
Subsignal
(
"cts"
,
Pins
(
"V19"
)),
Subsignal
(
"rts"
,
Pins
(
"W19"
)),
Subsignal
(
"rts"
,
Pins
(
"W19"
)),
Subsignal
(
"tx"
,
Pins
(
"U19"
)),
Subsignal
(
"tx"
,
Pins
(
"U19"
)),
Subsignal
(
"rx"
,
Pins
(
"T19"
)),
Subsignal
(
"rx"
,
Pins
(
"T19"
)),
IOStandard
(
"LVCMOS18"
)
IOStandard
(
"LVCMOS18"
)
),
),
...
@@ -39,38 +40,39 @@ _io = [
...
@@ -39,38 +40,39 @@ _io = [
),
),
(
"eth"
,
0
,
(
"eth"
,
0
,
Subsignal
(
"rx_ctl"
,
Pins
(
"U14"
)),
Subsignal
(
"rx_ctl"
,
Pins
(
"U14"
)),
Subsignal
(
"rx_data"
,
Pins
(
"U17 V17 V16 V14"
)),
Subsignal
(
"rx_data"
,
Pins
(
"U17 V17 V16 V14"
)),
Subsignal
(
"tx_ctl"
,
Pins
(
"T15"
)),
Subsignal
(
"tx_ctl"
,
Pins
(
"T15"
)),
Subsignal
(
"tx_data"
,
Pins
(
"U16 U15 T18 T17"
)),
Subsignal
(
"tx_data"
,
Pins
(
"U16 U15 T18 T17"
)),
Subsignal
(
"rst_n"
,
Pins
(
"V18"
)),
Subsignal
(
"rst_n"
,
Pins
(
"V18"
)),
Subsignal
(
"mdc"
,
Pins
(
"W18"
)),
Subsignal
(
"mdc"
,
Pins
(
"W18"
)),
Subsignal
(
"mdio"
,
Pins
(
"T14"
)),
Subsignal
(
"mdio"
,
Pins
(
"T14"
)),
IOStandard
(
"LVCMOS18"
),
Misc
(
"SLEW=FAST"
),
Drive
(
16
)
Misc
(
"SLEW=FAST"
),
Drive
(
16
),
IOStandard
(
"LVCMOS18"
),
),
),
(
"ddram"
,
0
,
(
"ddram"
,
0
,
Subsignal
(
"a"
,
Pins
(
Subsignal
(
"a"
,
Pins
(
"M4 J3 J1 L4 K5 M7 K1 M6"
,
"M4 J3 J1 L4 K5 M7 K1 M6"
,
"H1 K3 N7 L5 L7 N6 L3 K2"
),
"H1 K3 N7 L5 L7 N6 L3 K2"
),
IOStandard
(
"SSTL15"
)),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"ba"
,
Pins
(
"N1 M1 H2"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"ba"
,
Pins
(
"N1 M1 H2"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"ras_n"
,
Pins
(
"P1"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"ras_n"
,
Pins
(
"P1"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"cas_n"
,
Pins
(
"T4"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"cas_n"
,
Pins
(
"T4"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"we_n"
,
Pins
(
"R1"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"we_n"
,
Pins
(
"R1"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"cs_n"
,
Pins
(
"T3"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"cs_n"
,
Pins
(
"T3"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"dm"
,
Pins
(
"AC6 AC4 AA3 U7 G1 F3 G5 H9"
),
Subsignal
(
"dm"
,
Pins
(
"AC6 AC4 AA3 U7 G1 F3 G5 H9"
),
IOStandard
(
"SSTL15"
)),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"dq"
,
Pins
(
Subsignal
(
"dq"
,
Pins
(
"AB6 AA8 Y8 AB5 AA5 Y5 Y6 Y7"
,
"AB6 AA8
Y8 AB5 AA5
Y5
Y6
Y7"
,
"AF4 AF5 AF3 AE3 AD3 AC3 AB4 AA4"
,
"AF4 AF5 AF3 AE3 AD3 AC3 AB4 AA4"
,
"AC2 AB2 AF2 AE2 Y1 Y2 AC1 AB1"
,
"AC2 AB2 AF2 AE2
Y1
Y2 AC1 AB1"
,
"Y3 W3 W6 V6 W4 W5 W1 V1"
,
"Y3
W3
W6
V6
W4
W5
W1
V1"
,
"G2 D1 E1 E2 F2 A2 A3 C2"
,
"G2
D1
E1
E2
F2
A2
A3
C2"
,
"C3 D3 A4 B4 C4 D4 D5 E5"
,
"C3
D3
A4
B4
C4
D4
D5
E5"
,
"F4 G4 K6 K7 K8 L8 J5 J6"
,
"F4
G4
K6
K7
K8
L8
J5
J6"
,
"G6 H6 F7 F8 G8 H8 D6 E6"
),
"G6
H6
F7
F8
G8
H8
D6
E6"
),
IOStandard
(
"SSTL15"
),
IOStandard
(
"SSTL15"
),
Misc
(
"IN_TERM=UNTUNED_SPLIT_50"
)),
Misc
(
"IN_TERM=UNTUNED_SPLIT_50"
)),
Subsignal
(
"dqs_p"
,
Pins
(
"V8 AD5 AD1 V3 C1 B5 J4 H7"
),
Subsignal
(
"dqs_p"
,
Pins
(
"V8 AD5 AD1 V3 C1 B5 J4 H7"
),
...
@@ -79,8 +81,8 @@ _io = [
...
@@ -79,8 +81,8 @@ _io = [
IOStandard
(
"DIFF_SSTL15"
)),
IOStandard
(
"DIFF_SSTL15"
)),
Subsignal
(
"clk_p"
,
Pins
(
"M2"
),
IOStandard
(
"DIFF_SSTL15"
)),
Subsignal
(
"clk_p"
,
Pins
(
"M2"
),
IOStandard
(
"DIFF_SSTL15"
)),
Subsignal
(
"clk_n"
,
Pins
(
"L2"
),
IOStandard
(
"DIFF_SSTL15"
)),
Subsignal
(
"clk_n"
,
Pins
(
"L2"
),
IOStandard
(
"DIFF_SSTL15"
)),
Subsignal
(
"cke"
,
Pins
(
"P4"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"cke"
,
Pins
(
"P4"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"odt"
,
Pins
(
"R2"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"odt"
,
Pins
(
"R2"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"reset_n"
,
Pins
(
"N8"
),
IOStandard
(
"LVCMOS15"
)),
Subsignal
(
"reset_n"
,
Pins
(
"N8"
),
IOStandard
(
"LVCMOS15"
)),
Misc
(
"SLEW=FAST"
),
Misc
(
"SLEW=FAST"
),
),
),
...
@@ -89,10 +91,10 @@ _io = [
...
@@ -89,10 +91,10 @@ _io = [
Subsignal
(
"rst_n"
,
Pins
(
"M20"
),
IOStandard
(
"LVCMOS25"
)),
Subsignal
(
"rst_n"
,
Pins
(
"M20"
),
IOStandard
(
"LVCMOS25"
)),
Subsignal
(
"clk_p"
,
Pins
(
"F11"
)),
Subsignal
(
"clk_p"
,
Pins
(
"F11"
)),
Subsignal
(
"clk_n"
,
Pins
(
"E11"
)),
Subsignal
(
"clk_n"
,
Pins
(
"E11"
)),
Subsignal
(
"rx_p"
,
Pins
(
"D12"
)),
Subsignal
(
"rx_p"
,
Pins
(
"D12"
)),
Subsignal
(
"rx_n"
,
Pins
(
"C12"
)),
Subsignal
(
"rx_n"
,
Pins
(
"C12"
)),
Subsignal
(
"tx_p"
,
Pins
(
"D10"
)),
Subsignal
(
"tx_p"
,
Pins
(
"D10"
)),
Subsignal
(
"tx_n"
,
Pins
(
"C10"
))
Subsignal
(
"tx_n"
,
Pins
(
"C10"
))
),
),
(
"vadj_on_b"
,
0
,
Pins
(
"R16"
),
IOStandard
(
"LVCMOS25"
)),
(
"vadj_on_b"
,
0
,
Pins
(
"R16"
),
IOStandard
(
"LVCMOS25"
)),
...
@@ -111,97 +113,97 @@ _io = [
...
@@ -111,97 +113,97 @@ _io = [
(
"sfp_mgt_clk_sel0"
,
0
,
Pins
(
"B26"
),
IOStandard
(
"LVCMOS25"
)),
(
"sfp_mgt_clk_sel0"
,
0
,
Pins
(
"B26"
),
IOStandard
(
"LVCMOS25"
)),
(
"sfp_mgt_clk_sel1"
,
0
,
Pins
(
"C24"
),
IOStandard
(
"LVCMOS25"
)),
(
"sfp_mgt_clk_sel1"
,
0
,
Pins
(
"C24"
),
IOStandard
(
"LVCMOS25"
)),
(
"sfp_tx_disable_n"
,
0
,
Pins
(
"R18"
),
IOStandard
(
"LVCMOS33"
)),
(
"sfp_tx_disable_n"
,
0
,
Pins
(
"R18"
),
IOStandard
(
"LVCMOS33"
)),
(
"sfp_rx_los"
,
0
,
Pins
(
"R23"
),
IOStandard
(
"LVCMOS33"
)),
(
"sfp_rx_los"
,
0
,
Pins
(
"R23"
),
IOStandard
(
"LVCMOS33"
)),
]
]
# Connectors ---------------------------------------------------------------------------------------
# Connectors ---------------------------------------------------------------------------------------
_connectors
=
[
_connectors
=
[
(
"HPC"
,
{
(
"HPC"
,
{
"CLK0_M2C_N"
:
"C19"
,
"CLK0_M2C_N"
:
"C19"
,
"CLK0_M2C_P"
:
"D19"
,
"CLK0_M2C_P"
:
"D19"
,
"CLK1_M2C_N"
:
"H22"
,
"CLK1_M2C_N"
:
"H22"
,
"CLK1_M2C_P"
:
"H21"
,
"CLK1_M2C_P"
:
"H21"
,
"LA00_CC_N"
:
"C18"
,
"LA00_CC_N"
:
"C18"
,
"LA00_CC_P"
:
"D18"
,
"LA00_CC_P"
:
"D18"
,
"LA01_CC_N"
:
"E18"
,
"LA01_CC_N"
:
"E18"
,
"LA01_CC_P"
:
"E17"
,
"LA01_CC_P"
:
"E17"
,
"LA02_N"
:
"H15"
,
"LA02_N"
:
"H15"
,
"LA02_P"
:
"H14"
,
"LA02_P"
:
"H14"
,
"LA03_N"
:
"F17"
,
"LA03_N"
:
"F17"
,
"LA03_P"
:
"G17"
,
"LA03_P"
:
"G17"
,
"LA04_N"
:
"F19"
,
"LA04_N"
:
"F19"
,
"LA04_P"
:
"F18"
,
"LA04_P"
:
"F18"
,
"LA05_N"
:
"F15"
,
"LA05_N"
:
"F15"
,
"LA05_P"
:
"G15"
,
"LA05_P"
:
"G15"
,
"LA06_N"
:
"F20"
,
"LA06_N"
:
"F20"
,
"LA06_P"
:
"G19"
,
"LA06_P"
:
"G19"
,
"LA07_N"
:
"G16"
,
"LA07_N"
:
"G16"
,
"LA07_P"
:
"H16"
,
"LA07_P"
:
"H16"
,
"LA08_N"
:
"B17"
,
"LA08_N"
:
"B17"
,
"LA08_P"
:
"C17"
,
"LA08_P"
:
"C17"
,
"LA09_N"
:
"D16"
,
"LA09_N"
:
"D16"
,
"LA09_P"
:
"E16"
,
"LA09_P"
:
"E16"
,
"LA10_N"
:
"A18"
,
"LA10_N"
:
"A18"
,
"LA10_P"
:
"A17"
,
"LA10_P"
:
"A17"
,
"LA11_N"
:
"A19"
,
"LA11_N"
:
"A19"
,
"LA11_P"
:
"B19"
,
"LA11_P"
:
"B19"
,
"LA12_N"
:
"D20"
,
"LA12_N"
:
"D20"
,
"LA12_P"
:
"E20"
,
"LA12_P"
:
"E20"
,
"LA13_N"
:
"A20"
,
"LA13_N"
:
"A20"
,
"LA13_P"
:
"B20"
,
"LA13_P"
:
"B20"
,
"LA14_N"
:
"B21"
,
"LA14_N"
:
"B21"
,
"LA14_P"
:
"C21"
,
"LA14_P"
:
"C21"
,
"LA15_N"
:
"A22"
,
"LA15_N"
:
"A22"
,
"LA15_P"
:
"B22"
,
"LA15_P"
:
"B22"
,
"LA16_N"
:
"D21"
,
"LA16_N"
:
"D21"
,
"LA16_P"
:
"E21"
,
"LA16_P"
:
"E21"
,
"LA17_CC_N"
:
"J21"
,
"LA17_CC_N"
:
"J21"
,
"LA17_CC_P"
:
"K21"
,
"LA17_CC_P"
:
"K21"
,
"LA18_CC_N"
:
"G21"
,
"LA18_CC_N"
:
"G21"
,
"LA18_CC_P"
:
"G20"
,
"LA18_CC_P"
:
"G20"
,
"LA19_N"
:
"L14"
,
"LA19_N"
:
"L14"
,
"LA19_P"
:
"M14"
,
"LA19_P"
:
"M14"
,
"LA20_N"
:
"M17"
,
"LA20_N"
:
"M17"
,
"LA20_P"
:
"M16"
,
"LA20_P"
:
"M16"
,
"LA21_N"
:
"H19"
,
"LA21_N"
:
"H19"
,
"LA21_P"
:
"J19"
,
"LA21_P"
:
"J19"
,
"LA22_N"
:
"L18"
,
"LA22_N"
:
"L18"
,
"LA22_P"
:
"L17"
,
"LA22_P"
:
"L17"
,
"LA23_N"
:
"J20"
,
"LA23_N"
:
"J20"
,
"LA23_P"
:
"K20"
,
"LA23_P"
:
"K20"
,
"LA24_N"
:
"H18"
,
"LA24_N"
:
"H18"
,
"LA24_P"
:
"J18"
,
"LA24_P"
:
"J18"
,
"LA25_N"
:
"F22"
,
"LA25_N"
:
"F22"
,
"LA25_P"
:
"G22"
,
"LA25_P"
:
"G22"
,
"LA26_N"
:
"H24"
,
"LA26_N"
:
"H24"
,
"LA26_P"
:
"J24"
,
"LA26_P"
:
"J24"
,
"LA27_N"
:
"E23"
,
"LA27_N"
:
"E23"
,
"LA27_P"
:
"F23"
,
"LA27_P"
:
"F23"
,
"LA28_N"
:
"K23"
,
"LA28_N"
:
"K23"
,
"LA28_P"
:
"K22"
,
"LA28_P"
:
"K22"
,
"LA29_N"
:
"F24"
,
"LA29_N"
:
"F24"
,
"LA29_P"
:
"G24"
,
"LA29_P"
:
"G24"
,
"LA30_N"
:
"D25"
,
"LA30_N"
:
"D25"
,
"LA30_P"
:
"E25"
,
"LA30_P"
:
"E25"
,
"LA31_N"
:
"D26"
,
"LA31_N"
:
"D26"
,
"LA31_P"
:
"E26"
,
"LA31_P"
:
"E26"
,
"LA32_N"
:
"G26"
,
"LA32_N"
:
"G26"
,
"LA32_P"
:
"H26"
,
"LA32_P"
:
"H26"
,
"LA33_N"
:
"F25"
,
"LA33_N"
:
"F25"
,
"LA33_P"
:
"G25"
,
"LA33_P"
:
"G25"
,
"PRSNT_M2C_L"
:
"N16"
,
"PRSNT_M2C_L"
:
"N16"
,
"PWR_GOOD_FLASH_RST_B"
:
"P15"
}
"PWR_GOOD_FLASH_RST_B"
:
"P15"
}
),
),
(
"XADC"
,
{
(
"XADC"
,
{
"GPIO0"
:
"H17"
,
"GPIO0"
:
"H17"
,
"GPIO1"
:
"E22"
,
"GPIO1"
:
"E22"
,
"GPIO2"
:
"K18"
,
"GPIO2"
:
"K18"
,
"GPIO3"
:
"L19"
,
"GPIO3"
:
"L19"
,
"VAUX0_N"
:
"J16"
,
"VAUX0_N"
:
"J16"
,
"VAUX0_P"
:
"K15"
,
"VAUX0_P"
:
"K15"
,
"VAUX8_N"
:
"J15"
,
"VAUX8_N"
:
"J15"
,
"VAUX8_P"
:
"J14"
,
"VAUX8_P"
:
"J14"
,
}
}
),
),
]
]
...
@@ -209,7 +211,7 @@ _connectors = [
...
@@ -209,7 +211,7 @@ _connectors = [
# Platform -----------------------------------------------------------------------------------------
# Platform -----------------------------------------------------------------------------------------
class
Platform
(
XilinxPlatform
):
class
Platform
(
XilinxPlatform
):
default_clk_name
=
"clk156"
default_clk_name
=
"clk156"
default_clk_period
=
1e9
/
156.5e6
default_clk_period
=
1e9
/
156.5e6
def
__init__
(
self
):
def
__init__
(
self
):
...
@@ -221,19 +223,10 @@ class Platform(XilinxPlatform):
...
@@ -221,19 +223,10 @@ class Platform(XilinxPlatform):
self
.
add_platform_command
(
"set_property INTERNAL_VREF 0.750 [get_iobanks 35]"
)
self
.
add_platform_command
(
"set_property INTERNAL_VREF 0.750 [get_iobanks 35]"
)
def
create_programmer
(
self
):
def
create_programmer
(
self
):
return
VivadoProgrammer
(
)
return
OpenOCD
(
"openocd_xc7_ft2232.cfg"
,
"bscan_spi_xc7a200t.bit"
)
def
do_finalize
(
self
,
fragment
):
def
do_finalize
(
self
,
fragment
):
XilinxPlatform
.
do_finalize
(
self
,
fragment
)
XilinxPlatform
.
do_finalize
(
self
,
fragment
)
try
:
self
.
add_period_constraint
(
self
.
lookup_request
(
"clk200"
,
loose
=
True
),
1e9
/
200e6
)
self
.
add_period_constraint
(
self
.
lookup_request
(
"clk200"
).
p
,
1e9
/
200e6
)
self
.
add_period_constraint
(
self
.
lookup_request
(
"eth_clocks:rx"
,
loose
=
True
),
1e9
/
125e6
)
except
ConstraintError
:
self
.
add_period_constraint
(
self
.
lookup_request
(
"eth_clocks:tx"
,
loose
=
True
),
1e9
/
125e6
)
pass
try
:
self
.
add_period_constraint
(
self
.
lookup_request
(
"eth_clocks"
).
rx
,
1e9
/
125e6
)
except
ConstraintError
:
pass
try
:
self
.
add_period_constraint
(
self
.
lookup_request
(
"eth_clocks"
).
tx
,
1e9
/
125e6
)
except
ConstraintError
:
pass
This diff is collapsed.
Click to expand it.
litex_boards/platforms/acorn_cle_215.py
0 → 100644
View file @
a7d6de78
# This file is Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
# License: BSD
# The Acorn CLE 215+ is a cryptocurrency mining accelerator card from SQRL that can be repurposed
# as a generic FPGA PCIe development board: http://www.squirrelsresearch.com/acorn-cle-215-plus
from
litex.build.generic_platform
import
*
from
litex.build.xilinx
import
XilinxPlatform
from
litex.build.openocd
import
OpenOCD
# IOs ----------------------------------------------------------------------------------------------
_io
=
[
# clk / rst
(
"clk200"
,
0
,
Subsignal
(
"p"
,
Pins
(
"J19"
),
IOStandard
(
"DIFF_SSTL15"
)),
Subsignal
(
"n"
,
Pins
(
"H19"
),
IOStandard
(
"DIFF_SSTL15"
))
),
# leds
(
"user_led"
,
0
,
Pins
(
"G3"
),
IOStandard
(
"LVCMOS33"
)),
(
"user_led"
,
1
,
Pins
(
"H3"
),
IOStandard
(
"LVCMOS33"
)),
(
"user_led"
,
2
,
Pins
(
"G4"
),
IOStandard
(
"LVCMOS33"
)),
(
"user_led"
,
3
,
Pins
(
"H4"
),
IOStandard
(
"LVCMOS33"
)),
# spiflash
(
"spiflash"
,
0
,
Subsignal
(
"cs_n"
,
Pins
(
"T19"
)),
Subsignal
(
"mosi"
,
Pins
(
"P22"
)),
Subsignal
(
"miso"
,
Pins
(
"R22"
)),
Subsignal
(
"wp"
,
Pins
(
"P21"
)),
Subsignal
(
"hold"
,
Pins
(
"R21"
)),
IOStandard
(
"LVCMOS33"
)
),
# pcie
(
"pcie_clkreq_n"
,
0
,
Pins
(
"G1"
),
IOStandard
(
"LVCMOS33"
)),
(
"pcie_x4"
,
0
,
Subsignal
(
"rst_n"
,
Pins
(
"J1"
),
IOStandard
(
"LVCMOS33"
),
Misc
(
"PULLUP=TRUE"
)),
Subsignal
(
"clk_p"
,
Pins
(
"F6"
)),
Subsignal
(
"clk_n"
,
Pins
(
"E6"
)),
Subsignal
(
"rx_p"
,
Pins
(
"B10 B8 D11 D9"
)),
Subsignal
(
"rx_n"
,
Pins
(
"A10 A8 C11 C9"
)),
Subsignal
(
"tx_p"
,
Pins
(
"B6 B4 D5 D7"
)),
Subsignal
(
"tx_n"
,
Pins
(
"A6 A4 C5 C7"
)),
),
# dram
(
"ddram"
,
0
,
Subsignal
(
"a"
,
Pins
(
"M15 L21 M16 L18 K21 M18 M21 N20"
,
"M20 N19 J21 M22 K22 N18 N22 J22"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"ba"
,
Pins
(
"L19 J20 L20"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"ras_n"
,
Pins
(
"H20"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"cas_n"
,
Pins
(
"K18"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"we_n"
,
Pins
(
"L16"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"dm"
,
Pins
(
"A19 G22"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"dq"
,
Pins
(
"D19 B20 E19 A20 F19 C19 F20 C18"
,
"E22 G21 D20 E21 C22 D21 B22 D22"
),
IOStandard
(
"SSTL15"
),
Misc
(
"IN_TERM=UNTUNED_SPLIT_50"
)),
Subsignal
(
"dqs_p"
,
Pins
(
"F18 B21"
),
IOStandard
(
"DIFF_SSTL15"
)),
Subsignal
(
"dqs_n"
,
Pins
(
"E18 A21"
),
IOStandard
(
"DIFF_SSTL15"
)),
Subsignal
(
"clk_p"
,
Pins
(
"K17"
),
IOStandard
(
"DIFF_SSTL15"
)),
Subsignal
(
"clk_n"
,
Pins
(
"J17"
),
IOStandard
(
"DIFF_SSTL15"
)),
Subsignal
(
"cke"
,
Pins
(
"H22"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"odt"
,
Pins
(
"K19"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"reset_n"
,
Pins
(
"K16"
),
IOStandard
(
"LVCMOS15"
)),
#Subsignal("cs_n", Pins(""), IOStandard("SSTL15")),
Misc
(
"SLEW=FAST"
),
),
]
# Platform -----------------------------------------------------------------------------------------
class
Platform
(
XilinxPlatform
):
default_clk_name
=
"clk200"
default_clk_period
=
1e9
/
200e6
def
__init__
(
self
):
XilinxPlatform
.
__init__
(
self
,
"xc7a200t-fbg484-2"
,
_io
,
toolchain
=
"vivado"
)
self
.
add_platform_command
(
"set_property INTERNAL_VREF 0.750 [get_iobanks 34]"
)
self
.
toolchain
.
bitstream_commands
=
[
"set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"
,
"set_property BITSTREAM.CONFIG.CONFIGRATE 16 [current_design]"
,
"set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]"
]
self
.
toolchain
.
additional_commands
=
\
[
"write_cfgmem -force -format bin -interface spix4 -size 16 "
"-loadbit
\"
up 0x0 {build_name}.bit
\"
-file {build_name}.bin"
]
def
create_programmer
(
self
):
return
OpenOCD
(
"openocd_xc7_ft232.cfg"
,
"bscan_spi_xc7a200t.bit"
)
def
do_finalize
(
self
,
fragment
):
XilinxPlatform
.
do_finalize
(
self
,
fragment
)
self
.
add_period_constraint
(
self
.
lookup_request
(
"clk200"
,
loose
=
True
),
1e9
/
200e6
)
This diff is collapsed.
Click to expand it.
litex_boards/
partner/
platforms/aller.py
→
litex_boards/platforms/aller.py
View file @
a7d6de78
...
@@ -4,6 +4,7 @@
...
@@ -4,6 +4,7 @@
from
litex.build.generic_platform
import
*
from
litex.build.generic_platform
import
*
from
litex.build.xilinx
import
XilinxPlatform
from
litex.build.xilinx
import
XilinxPlatform
from
litex.build.openocd
import
OpenOCD
# IOs ----------------------------------------------------------------------------------------------
# IOs ----------------------------------------------------------------------------------------------
...
@@ -14,7 +15,7 @@ _io = [
...
@@ -14,7 +15,7 @@ _io = [
# leds (only a single rgb led, aliased here also)
# leds (only a single rgb led, aliased here also)
(
"user_led"
,
0
,
Pins
(
"AB21"
),
IOStandard
(
"LVCMOS33"
)),
(
"user_led"
,
0
,
Pins
(
"AB21"
),
IOStandard
(
"LVCMOS33"
)),
(
"user_led"
,
1
,
Pins
(
"AB22"
),
IOStandard
(
"LVCMOS33"
)),
(
"user_led"
,
1
,
Pins
(
"AB22"
),
IOStandard
(
"LVCMOS33"
)),
(
"user_led"
,
2
,
Pins
(
"U20"
),
IOStandard
(
"LVCMOS33"
)),
(
"user_led"
,
2
,
Pins
(
"U20"
),
IOStandard
(
"LVCMOS33"
)),
# rgb led, active-low
# rgb led, active-low
(
"rgb_led"
,
0
,
(
"rgb_led"
,
0
,
...
@@ -26,75 +27,73 @@ _io = [
...
@@ -26,75 +27,73 @@ _io = [
# flash
# flash
(
"flash"
,
0
,
(
"flash"
,
0
,
Subsignal
(
"cs_n"
,
Pins
(
"T19"
)),
Subsignal
(
"cs_n"
,
Pins
(
"T19"
)),
Subsignal
(
"mosi"
,
Pins
(
"P22"
)),
Subsignal
(
"mosi"
,
Pins
(
"P22"
)),
Subsignal
(
"miso"
,
Pins
(
"R22"
)),
Subsignal
(
"miso"
,
Pins
(
"R22"
)),
Subsignal
(
"hold"
,
Pins
(
"R21"
)),
Subsignal
(
"hold"
,
Pins
(
"R21"
)),
Subsignal
(
"rst_n"
,
Pins
(
"R19"
)),
Subsignal
(
"rst_n"
,
Pins
(
"R19"
)),
IOStandard
(
"LVCMOS33"
)
IOStandard
(
"LVCMOS33"
)
),
),
(
"flash4x"
,
0
,
# clock needs to be accessed through STARTUPE2
(
"flash4x"
,
0
,
# clock needs to be accessed through STARTUPE2
Subsignal
(
"cs_n"
,
Pins
(
"T19"
)),
Subsignal
(
"cs_n"
,
Pins
(
"T19"
)),
Subsignal
(
"dq"
,
Pins
(
"P22"
,
"R22"
,
"P21"
,
"R21"
)),
Subsignal
(
"dq"
,
Pins
(
"P22"
,
"R22"
,
"P21"
,
"R21"
)),
IOStandard
(
"LVCMOS33"
)
IOStandard
(
"LVCMOS33"
)
),
),
# tpm
# tpm
(
"tpm"
,
0
,
(
"tpm"
,
0
,
Subsignal
(
"clk"
,
Pins
(
"W20"
)),
Subsignal
(
"clk"
,
Pins
(
"W20"
)),
Subsignal
(
"rst_n"
,
Pins
(
"V19"
)),
Subsignal
(
"rst_n"
,
Pins
(
"V19"
)),
Subsignal
(
"cs_n"
,
Pins
(
"Y18"
)),
Subsignal
(
"cs_n"
,
Pins
(
"Y18"
)),
Subsignal
(
"mosi"
,
Pins
(
"Y19"
)),
Subsignal
(
"mosi"
,
Pins
(
"Y19"
)),
Subsignal
(
"miso"
,
Pins
(
"V18"
)),
Subsignal
(
"miso"
,
Pins
(
"V18"
)),
IOStandard
(
"LVCMOS33"
),
IOStandard
(
"LVCMOS33"
),
),
),
# pcie
# pcie
(
"pcie"
,
0
,
(
"pcie
_x1
"
,
0
,
Subsignal
(
"rst_n"
,
Pins
(
"AB20"
),
IOStandard
(
"LVCMOS33"
),
Misc
(
"PULLUP=TRUE"
)),
Subsignal
(
"rst_n"
,
Pins
(
"AB20"
),
IOStandard
(
"LVCMOS33"
),
Misc
(
"PULLUP=TRUE"
)),
Subsignal
(
"clk_p"
,
Pins
(
"F6"
)),
Subsignal
(
"clk_p"
,
Pins
(
"F6"
)),
Subsignal
(
"clk_n"
,
Pins
(
"E6"
)),
Subsignal
(
"clk_n"
,
Pins
(
"E6"
)),
Subsignal
(
"rx_p"
,
Pins
(
"B8
D11 B10 D9
"
)),
Subsignal
(
"rx_p"
,
Pins
(
"B8"
)),
Subsignal
(
"rx_n"
,
Pins
(
"A8
C11 A10 C9
"
)),
Subsignal
(
"rx_n"
,
Pins
(
"A8"
)),
Subsignal
(
"tx_p"
,
Pins
(
"B4
D5 B6 D7
"
)),
Subsignal
(
"tx_p"
,
Pins
(
"B4"
)),
Subsignal
(
"tx_n"
,
Pins
(
"A4
C5 A6 C7
"
))
Subsignal
(
"tx_n"
,
Pins
(
"A4"
))
),
),
(
"pcie_x
1
"
,
0
,
(
"pcie_x
4
"
,
0
,
Subsignal
(
"rst_n"
,
Pins
(
"AB20"
),
IOStandard
(
"LVCMOS33"
),
Misc
(
"PULLUP=TRUE"
)),
Subsignal
(
"rst_n"
,
Pins
(
"AB20"
),
IOStandard
(
"LVCMOS33"
),
Misc
(
"PULLUP=TRUE"
)),
Subsignal
(
"clk_p"
,
Pins
(
"F6"
)),
Subsignal
(
"clk_p"
,
Pins
(
"F6"
)),
Subsignal
(
"clk_n"
,
Pins
(
"E6"
)),
Subsignal
(
"clk_n"
,
Pins
(
"E6"
)),
Subsignal
(
"rx_p"
,
Pins
(
"B8"
)),
Subsignal
(
"rx_p"
,
Pins
(
"B8
D11 B10 D9
"
)),
Subsignal
(
"rx_n"
,
Pins
(
"A8"
)),
Subsignal
(
"rx_n"
,
Pins
(
"A8
C11 A10 C9
"
)),
Subsignal
(
"tx_p"
,
Pins
(
"B4"
)),
Subsignal
(
"tx_p"
,
Pins
(
"B4
D5 B6 D7
"
)),
Subsignal
(
"tx_n"
,
Pins
(
"A4"
))
Subsignal
(
"tx_n"
,
Pins
(
"A4
C5 A6 C7
"
))
),
),
# dram
# dram
(
"ddram"
,
0
,
(
"ddram"
,
0
,
Subsignal
(
"a"
,
Pins
(
Subsignal
(
"a"
,
Pins
(
"U6 T5 Y6 T6 V2 T4 Y2 R2"
,
"U6 T5 Y6 T6 V2 T4 Y2 R2"
,
"Y1 R4 W5 W1 AA6 U2"
"Y1 R4 W5 W1 AA6 U2"
),
),
IOStandard
(
"SSTL15"
)),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"ba"
,
Pins
(
"W6 U5 R6"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"ba"
,
Pins
(
"W6 U5 R6"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"ras_n"
,
Pins
(
"V5"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"ras_n"
,
Pins
(
"V5"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"cas_n"
,
Pins
(
"T1"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"cas_n"
,
Pins
(
"T1"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"we_n"
,
Pins
(
"R3"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"we_n"
,
Pins
(
"R3"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"dm"
,
Pins
(
"Y7 AA1"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"dm"
,
Pins
(
"Y7 AA1"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"dq"
,
Pins
(
Subsignal
(
"dq"
,
Pins
(
"Y8 AB6 W9 AA8 AB7 V7 AB8 W7"
,
"Y8 AB6 W9 AA8 AB7 V7 AB8 W7"
,
"V4 AB2 AA5 AB3 AB5 W4 AB1 AA4"
"V4 AB2 AA5 AB3 AB5 W4 AB1 AA4"
),
),
IOStandard
(
"SSTL15"
),
IOStandard
(
"SSTL15"
),
Misc
(
"IN_TERM=UNTUNED_SPLIT_50"
)),
Misc
(
"IN_TERM=UNTUNED_SPLIT_50"
)),
Subsignal
(
"dqs_p"
,
Pins
(
"V9 Y3"
),
IOStandard
(
"DIFF_SSTL15"
)),
Subsignal
(
"dqs_p"
,
Pins
(
"V9 Y3"
),
IOStandard
(
"DIFF_SSTL15"
)),
Subsignal
(
"dqs_n"
,
Pins
(
"V8 AA3"
),
IOStandard
(
"DIFF_SSTL15"
)),
Subsignal
(
"dqs_n"
,
Pins
(
"V8 AA3"
),
IOStandard
(
"DIFF_SSTL15"
)),
Subsignal
(
"clk_p"
,
Pins
(
"U3"
),
IOStandard
(
"DIFF_SSTL15"
)),
Subsignal
(
"clk_p"
,
Pins
(
"U3"
),
IOStandard
(
"DIFF_SSTL15"
)),
Subsignal
(
"clk_n"
,
Pins
(
"V3"
),
IOStandard
(
"DIFF_SSTL15"
)),
Subsignal
(
"clk_n"
,
Pins
(
"V3"
),
IOStandard
(
"DIFF_SSTL15"
)),
Subsignal
(
"cke"
,
Pins
(
"U1"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"cke"
,
Pins
(
"U1"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"odt"
,
Pins
(
"W2"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"odt"
,
Pins
(
"W2"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"reset_n"
,
Pins
(
"U7"
),
IOStandard
(
"LVCMOS15"
)),
Subsignal
(
"reset_n"
,
Pins
(
"U7"
),
IOStandard
(
"LVCMOS15"
)),
Subsignal
(
"cs_n"
,
Pins
(
"T3"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"cs_n"
,
Pins
(
"T3"
),
IOStandard
(
"SSTL15"
)),
Misc
(
"SLEW=FAST"
),
Misc
(
"SLEW=FAST"
),
...
@@ -104,7 +103,7 @@ _io = [
...
@@ -104,7 +103,7 @@ _io = [
# Platform -----------------------------------------------------------------------------------------
# Platform -----------------------------------------------------------------------------------------
class
Platform
(
XilinxPlatform
):
class
Platform
(
XilinxPlatform
):
default_clk_name
=
"clk100"
default_clk_name
=
"clk100"
default_clk_period
=
1e9
/
100e6
default_clk_period
=
1e9
/
100e6
def
__init__
(
self
):
def
__init__
(
self
):
...
@@ -118,3 +117,10 @@ class Platform(XilinxPlatform):
...
@@ -118,3 +117,10 @@ class Platform(XilinxPlatform):
self
.
toolchain
.
additional_commands
=
\
self
.
toolchain
.
additional_commands
=
\
[
"write_cfgmem -force -format bin -interface spix4 -size 16 "
[
"write_cfgmem -force -format bin -interface spix4 -size 16 "
"-loadbit
\"
up 0x0 {build_name}.bit
\"
-file {build_name}.bin"
]
"-loadbit
\"
up 0x0 {build_name}.bit
\"
-file {build_name}.bin"
]
def
create_programmer
(
self
):
return
OpenOCD
(
"openocd_xc7_ft232.cfg"
,
"bscan_spi_xc7a200t.bit"
)
def
do_finalize
(
self
,
fragment
):
XilinxPlatform
.
do_finalize
(
self
,
fragment
)
self
.
add_period_constraint
(
self
.
lookup_request
(
"clk100"
,
loose
=
True
),
1e9
/
100e6
)
This diff is collapsed.
Click to expand it.
litex_boards/
official/
platforms/arty.py
→
litex_boards/platforms/arty.py
View file @
a7d6de78
...
@@ -3,14 +3,15 @@
...
@@ -3,14 +3,15 @@
# License: BSD
# License: BSD
from
litex.build.generic_platform
import
*
from
litex.build.generic_platform
import
*
from
litex.build.xilinx
import
XilinxPlatform
,
VivadoProgrammer
from
litex.build.xilinx
import
XilinxPlatform
from
litex.build.openocd
import
OpenOCD
# IOs ----------------------------------------------------------------------------------------------
# IOs ----------------------------------------------------------------------------------------------
_io
=
[
_io
=
[
(
"user_led"
,
0
,
Pins
(
"H5"
),
IOStandard
(
"LVCMOS33"
)),
(
"user_led"
,
0
,
Pins
(
"H5"
),
IOStandard
(
"LVCMOS33"
)),
(
"user_led"
,
1
,
Pins
(
"J5"
),
IOStandard
(
"LVCMOS33"
)),
(
"user_led"
,
1
,
Pins
(
"J5"
),
IOStandard
(
"LVCMOS33"
)),
(
"user_led"
,
2
,
Pins
(
"T9"
),
IOStandard
(
"LVCMOS33"
)),
(
"user_led"
,
2
,
Pins
(
"T9"
),
IOStandard
(
"LVCMOS33"
)),
(
"user_led"
,
3
,
Pins
(
"T10"
),
IOStandard
(
"LVCMOS33"
)),
(
"user_led"
,
3
,
Pins
(
"T10"
),
IOStandard
(
"LVCMOS33"
)),
(
"rgb_led"
,
0
,
(
"rgb_led"
,
0
,
...
@@ -41,7 +42,7 @@ _io = [
...
@@ -41,7 +42,7 @@ _io = [
IOStandard
(
"LVCMOS33"
),
IOStandard
(
"LVCMOS33"
),
),
),
(
"user_sw"
,
0
,
Pins
(
"A8"
),
IOStandard
(
"LVCMOS33"
)),
(
"user_sw"
,
0
,
Pins
(
"A8"
),
IOStandard
(
"LVCMOS33"
)),
(
"user_sw"
,
1
,
Pins
(
"C11"
),
IOStandard
(
"LVCMOS33"
)),
(
"user_sw"
,
1
,
Pins
(
"C11"
),
IOStandard
(
"LVCMOS33"
)),
(
"user_sw"
,
2
,
Pins
(
"C10"
),
IOStandard
(
"LVCMOS33"
)),
(
"user_sw"
,
2
,
Pins
(
"C10"
),
IOStandard
(
"LVCMOS33"
)),
(
"user_sw"
,
3
,
Pins
(
"A10"
),
IOStandard
(
"LVCMOS33"
)),
(
"user_sw"
,
3
,
Pins
(
"A10"
),
IOStandard
(
"LVCMOS33"
)),
...
@@ -62,7 +63,7 @@ _io = [
...
@@ -62,7 +63,7 @@ _io = [
),
),
(
"spi"
,
0
,
(
"spi"
,
0
,
Subsignal
(
"clk"
,
Pins
(
"F1"
)),
Subsignal
(
"clk"
,
Pins
(
"F1"
)),
Subsignal
(
"cs_n"
,
Pins
(
"C1"
)),
Subsignal
(
"cs_n"
,
Pins
(
"C1"
)),
Subsignal
(
"mosi"
,
Pins
(
"H1"
)),
Subsignal
(
"mosi"
,
Pins
(
"H1"
)),
Subsignal
(
"miso"
,
Pins
(
"G1"
)),
Subsignal
(
"miso"
,
Pins
(
"G1"
)),
...
@@ -79,16 +80,16 @@ _io = [
...
@@ -79,16 +80,16 @@ _io = [
(
"spiflash4x"
,
0
,
(
"spiflash4x"
,
0
,
Subsignal
(
"cs_n"
,
Pins
(
"L13"
)),
Subsignal
(
"cs_n"
,
Pins
(
"L13"
)),
Subsignal
(
"clk"
,
Pins
(
"L16"
)),
Subsignal
(
"clk"
,
Pins
(
"L16"
)),
Subsignal
(
"dq"
,
Pins
(
"K17"
,
"K18"
,
"L14"
,
"M14"
)),
Subsignal
(
"dq"
,
Pins
(
"K17"
,
"K18"
,
"L14"
,
"M14"
)),
IOStandard
(
"LVCMOS33"
)
IOStandard
(
"LVCMOS33"
)
),
),
(
"spiflash"
,
0
,
(
"spiflash"
,
0
,
Subsignal
(
"cs_n"
,
Pins
(
"L13"
)),
Subsignal
(
"cs_n"
,
Pins
(
"L13"
)),
Subsignal
(
"clk"
,
Pins
(
"L16"
)),
Subsignal
(
"clk"
,
Pins
(
"L16"
)),
Subsignal
(
"mosi"
,
Pins
(
"K17"
)),
Subsignal
(
"mosi"
,
Pins
(
"K17"
)),
Subsignal
(
"miso"
,
Pins
(
"K18"
)),
Subsignal
(
"miso"
,
Pins
(
"K18"
)),
Subsignal
(
"wp"
,
Pins
(
"L14"
)),
Subsignal
(
"wp"
,
Pins
(
"L14"
)),
Subsignal
(
"hold"
,
Pins
(
"M14"
)),
Subsignal
(
"hold"
,
Pins
(
"M14"
)),
IOStandard
(
"LVCMOS33"
),
IOStandard
(
"LVCMOS33"
),
),
),
...
@@ -98,23 +99,27 @@ _io = [
...
@@ -98,23 +99,27 @@ _io = [
"R2 M6 N4 T1 N6 R7 V6 U7"
,
"R2 M6 N4 T1 N6 R7 V6 U7"
,
"R8 V7 R6 U6 T6 T8"
),
"R8 V7 R6 U6 T6 T8"
),
IOStandard
(
"SSTL135"
)),
IOStandard
(
"SSTL135"
)),
Subsignal
(
"ba"
,
Pins
(
"R1 P4 P2"
),
IOStandard
(
"SSTL135"
)),
Subsignal
(
"ba"
,
Pins
(
"R1 P4 P2"
),
IOStandard
(
"SSTL135"
)),
Subsignal
(
"ras_n"
,
Pins
(
"P3"
),
IOStandard
(
"SSTL135"
)),
Subsignal
(
"ras_n"
,
Pins
(
"P3"
),
IOStandard
(
"SSTL135"
)),
Subsignal
(
"cas_n"
,
Pins
(
"M4"
),
IOStandard
(
"SSTL135"
)),
Subsignal
(
"cas_n"
,
Pins
(
"M4"
),
IOStandard
(
"SSTL135"
)),
Subsignal
(
"we_n"
,
Pins
(
"P5"
),
IOStandard
(
"SSTL135"
)),
Subsignal
(
"we_n"
,
Pins
(
"P5"
),
IOStandard
(
"SSTL135"
)),
Subsignal
(
"cs_n"
,
Pins
(
"U8"
),
IOStandard
(
"SSTL135"
)),
Subsignal
(
"cs_n"
,
Pins
(
"U8"
),
IOStandard
(
"SSTL135"
)),
Subsignal
(
"dm"
,
Pins
(
"L1 U1"
),
IOStandard
(
"SSTL135"
)),
Subsignal
(
"dm"
,
Pins
(
"L1 U1"
),
IOStandard
(
"SSTL135"
)),
Subsignal
(
"dq"
,
Pins
(
Subsignal
(
"dq"
,
Pins
(
"K5 L3 K3 L6 M3 M1 L4 M2"
,
"K5 L3 K3 L6 M3 M1 L4 M2"
,
"V4 T5 U4 V5 V1 T3 U3 R3"
),
"V4 T5 U4 V5 V1 T3 U3 R3"
),
IOStandard
(
"SSTL135"
),
IOStandard
(
"SSTL135"
),
Misc
(
"IN_TERM=UNTUNED_SPLIT_40"
)),
Misc
(
"IN_TERM=UNTUNED_SPLIT_40"
)),
Subsignal
(
"dqs_p"
,
Pins
(
"N2 U2"
),
IOStandard
(
"DIFF_SSTL135"
)),
Subsignal
(
"dqs_p"
,
Pins
(
"N2 U2"
),
Subsignal
(
"dqs_n"
,
Pins
(
"N1 V2"
),
IOStandard
(
"DIFF_SSTL135"
)),
IOStandard
(
"DIFF_SSTL135"
),
Misc
(
"IN_TERM=UNTUNED_SPLIT_40"
)),
Subsignal
(
"dqs_n"
,
Pins
(
"N1 V2"
),
IOStandard
(
"DIFF_SSTL135"
),
Misc
(
"IN_TERM=UNTUNED_SPLIT_40"
)),
Subsignal
(
"clk_p"
,
Pins
(
"U9"
),
IOStandard
(
"DIFF_SSTL135"
)),
Subsignal
(
"clk_p"
,
Pins
(
"U9"
),
IOStandard
(
"DIFF_SSTL135"
)),
Subsignal
(
"clk_n"
,
Pins
(
"V9"
),
IOStandard
(
"DIFF_SSTL135"
)),
Subsignal
(
"clk_n"
,
Pins
(
"V9"
),
IOStandard
(
"DIFF_SSTL135"
)),
Subsignal
(
"cke"
,
Pins
(
"N5"
),
IOStandard
(
"SSTL135"
)),
Subsignal
(
"cke"
,
Pins
(
"N5"
),
IOStandard
(
"SSTL135"
)),
Subsignal
(
"odt"
,
Pins
(
"R5"
),
IOStandard
(
"SSTL135"
)),
Subsignal
(
"odt"
,
Pins
(
"R5"
),
IOStandard
(
"SSTL135"
)),
Subsignal
(
"reset_n"
,
Pins
(
"K6"
),
IOStandard
(
"SSTL135"
)),
Subsignal
(
"reset_n"
,
Pins
(
"K6"
),
IOStandard
(
"SSTL135"
)),
Misc
(
"SLEW=FAST"
),
Misc
(
"SLEW=FAST"
),
),
),
...
@@ -126,16 +131,16 @@ _io = [
...
@@ -126,16 +131,16 @@ _io = [
IOStandard
(
"LVCMOS33"
),
IOStandard
(
"LVCMOS33"
),
),
),
(
"eth"
,
0
,
(
"eth"
,
0
,
Subsignal
(
"rst_n"
,
Pins
(
"C16"
)),
Subsignal
(
"rst_n"
,
Pins
(
"C16"
)),
Subsignal
(
"mdio"
,
Pins
(
"K13"
)),
Subsignal
(
"mdio"
,
Pins
(
"K13"
)),
Subsignal
(
"mdc"
,
Pins
(
"F16"
)),
Subsignal
(
"mdc"
,
Pins
(
"F16"
)),
Subsignal
(
"rx_dv"
,
Pins
(
"G16"
)),
Subsignal
(
"rx_dv"
,
Pins
(
"G16"
)),
Subsignal
(
"rx_er"
,
Pins
(
"C17"
)),
Subsignal
(
"rx_er"
,
Pins
(
"C17"
)),
Subsignal
(
"rx_data"
,
Pins
(
"D18 E17 E18 G17"
)),
Subsignal
(
"rx_data"
,
Pins
(
"D18 E17 E18 G17"
)),
Subsignal
(
"tx_en"
,
Pins
(
"H15"
)),
Subsignal
(
"tx_en"
,
Pins
(
"H15"
)),
Subsignal
(
"tx_data"
,
Pins
(
"H14 J14 J13 H17"
)),
Subsignal
(
"tx_data"
,
Pins
(
"H14 J14 J13 H17"
)),
Subsignal
(
"col"
,
Pins
(
"D17"
)),
Subsignal
(
"col"
,
Pins
(
"D17"
)),
Subsignal
(
"crs"
,
Pins
(
"G14"
)),
Subsignal
(
"crs"
,
Pins
(
"G14"
)),
IOStandard
(
"LVCMOS33"
),
IOStandard
(
"LVCMOS33"
),
),
),
]
]
...
@@ -149,16 +154,16 @@ _connectors = [
...
@@ -149,16 +154,16 @@ _connectors = [
(
"pmodd"
,
"D4 D3 F4 F3 E2 D2 H2 G2"
),
(
"pmodd"
,
"D4 D3 F4 F3 E2 D2 H2 G2"
),
(
"ck_io"
,
{
(
"ck_io"
,
{
# Outer Digital Header
# Outer Digital Header
"ck_io0"
:
"V15"
,
"ck_io0"
:
"V15"
,
"ck_io1"
:
"U16"
,
"ck_io1"
:
"U16"
,
"ck_io2"
:
"P14"
,
"ck_io2"
:
"P14"
,
"ck_io3"
:
"T11"
,
"ck_io3"
:
"T11"
,
"ck_io4"
:
"R12"
,
"ck_io4"
:
"R12"
,
"ck_io5"
:
"T14"
,
"ck_io5"
:
"T14"
,
"ck_io6"
:
"T15"
,
"ck_io6"
:
"T15"
,
"ck_io7"
:
"T16"
,
"ck_io7"
:
"T16"
,
"ck_io8"
:
"N15"
,
"ck_io8"
:
"N15"
,
"ck_io9"
:
"M16"
,
"ck_io9"
:
"M16"
,
"ck_io10"
:
"V17"
,
"ck_io10"
:
"V17"
,
"ck_io11"
:
"U18"
,
"ck_io11"
:
"U18"
,
"ck_io12"
:
"R17"
,
"ck_io12"
:
"R17"
,
...
@@ -200,18 +205,18 @@ _connectors = [
...
@@ -200,18 +205,18 @@ _connectors = [
}
),
}
),
(
"XADC"
,
{
(
"XADC"
,
{
# Outer Analog Header
# Outer Analog Header
"vaux4_n"
:
"C5"
,
"vaux4_n"
:
"C5"
,
"vaux4_p"
:
"C6"
,
"vaux4_p"
:
"C6"
,
"vaux5_n"
:
"A5"
,
"vaux5_n"
:
"A5"
,
"vaux5_p"
:
"A6"
,
"vaux5_p"
:
"A6"
,
"vaux6_n"
:
"B4"
,
"vaux6_n"
:
"B4"
,
"vaux6_p"
:
"C4"
,
"vaux6_p"
:
"C4"
,
"vaux7_n"
:
"A1"
,
"vaux7_n"
:
"A1"
,
"vaux7_p"
:
"B1"
,
"vaux7_p"
:
"B1"
,
"vaux15_n"
:
"B2"
,
"vaux15_n"
:
"B2"
,
"vaux15_p"
:
"B3"
,
"vaux15_p"
:
"B3"
,
"vaux0_n"
:
"C14"
,
"vaux0_n"
:
"C14"
,
"vaux0_p"
:
"D14"
,
"vaux0_p"
:
"D14"
,
# Inner Analog Header
# Inner Analog Header
"vaux12_n"
:
"B7"
,
"vaux12_n"
:
"B7"
,
...
@@ -222,12 +227,12 @@ _connectors = [
...
@@ -222,12 +227,12 @@ _connectors = [
"vaux14_p"
:
"A3"
,
"vaux14_p"
:
"A3"
,
# Power Measurements
# Power Measurements
"vsnsuv_n"
:
"B17"
,
"vsnsuv_n"
:
"B17"
,
"vsnsuv_p"
:
"B16"
,
"vsnsuv_p"
:
"B16"
,
"vsns5v0_n"
:
"B12"
,
"vsns5v0_n"
:
"B12"
,
"vsns5v0_p"
:
"C12"
,
"vsns5v0_p"
:
"C12"
,
"isns5v0_n"
:
"F14"
,
"isns5v0_n"
:
"F14"
,
"isns5v0_n"
:
"F13"
,
"isns5v0_n"
:
"F13"
,
"isns0v95_n"
:
"A16"
,
"isns0v95_n"
:
"A16"
,
"isns0v95_n"
:
"A15"
,
"isns0v95_n"
:
"A15"
,
}
),
}
),
...
@@ -236,7 +241,7 @@ _connectors = [
...
@@ -236,7 +241,7 @@ _connectors = [
# Platform -----------------------------------------------------------------------------------------
# Platform -----------------------------------------------------------------------------------------
class
Platform
(
XilinxPlatform
):
class
Platform
(
XilinxPlatform
):
default_clk_name
=
"clk100"
default_clk_name
=
"clk100"
default_clk_period
=
1e9
/
100e6
default_clk_period
=
1e9
/
100e6
def
__init__
(
self
,
variant
=
"a7-35"
):
def
__init__
(
self
,
variant
=
"a7-35"
):
...
@@ -253,4 +258,9 @@ class Platform(XilinxPlatform):
...
@@ -253,4 +258,9 @@ class Platform(XilinxPlatform):
self
.
add_platform_command
(
"set_property INTERNAL_VREF 0.675 [get_iobanks 34]"
)
self
.
add_platform_command
(
"set_property INTERNAL_VREF 0.675 [get_iobanks 34]"
)
def
create_programmer
(
self
):
def
create_programmer
(
self
):
return
VivadoProgrammer
(
flash_part
=
"n25q128-3.3v-spi-x1_x2_x4"
)
bscan_spi
=
"bscan_spi_xc7a100t.bit"
if
"xc7a100t"
in
self
.
device
else
"bscan_spi_xc7a35t.bit"
return
OpenOCD
(
"openocd_xc7_ft2232.cfg"
,
bscan_spi
)
def
do_finalize
(
self
,
fragment
):
XilinxPlatform
.
do_finalize
(
self
,
fragment
)
self
.
add_period_constraint
(
self
.
lookup_request
(
"clk100"
,
loose
=
True
),
1e9
/
100e6
)
This diff is collapsed.
Click to expand it.
litex_boards/platforms/arty_s7.py
0 → 100644
View file @
a7d6de78
# This file is Copyright (c) 2018 William D. Jones <thor0505@comcast.net>
# This file is Copyright (c) 2020 Staf Verhaegen <staf@fibraservi.eu>
# License: BSD
from
litex.build.generic_platform
import
Pins
,
Subsignal
,
IOStandard
,
Misc
from
litex.build.xilinx
import
XilinxPlatform
from
litex.build.openocd
import
OpenOCD
# IOs ----------------------------------------------------------------------------------------------
_io
=
[
(
"user_led"
,
0
,
Pins
(
"E18"
),
IOStandard
(
"LVCMOS33"
)),
(
"user_led"
,
1
,
Pins
(
"F13"
),
IOStandard
(
"LVCMOS33"
)),
(
"user_led"
,
2
,
Pins
(
"E13"
),
IOStandard
(
"LVCMOS33"
)),
(
"user_led"
,
3
,
Pins
(
"H15"
),
IOStandard
(
"LVCMOS33"
)),
(
"rgb_led"
,
0
,
Subsignal
(
"r"
,
Pins
(
"J15"
)),
Subsignal
(
"g"
,
Pins
(
"G17"
)),
Subsignal
(
"b"
,
Pins
(
"F15"
)),
IOStandard
(
"LVCMOS33"
)
),
(
"rgb_led"
,
1
,
Subsignal
(
"r"
,
Pins
(
"E15"
)),
Subsignal
(
"g"
,
Pins
(
"F18"
)),
Subsignal
(
"b"
,
Pins
(
"E14"
)),
IOStandard
(
"LVCMOS33"
)
),
(
"user_sw"
,
0
,
Pins
(
"H14"
),
IOStandard
(
"LVCMOS33"
)),
(
"user_sw"
,
1
,
Pins
(
"H18"
),
IOStandard
(
"LVCMOS33"
)),
(
"user_sw"
,
2
,
Pins
(
"G18"
),
IOStandard
(
"LVCMOS33"
)),
(
"user_sw"
,
3
,
Pins
(
"M5"
),
IOStandard
(
"SSTL135"
)),
(
"user_btn"
,
0
,
Pins
(
"G15"
),
IOStandard
(
"LVCMOS33"
)),
(
"user_btn"
,
1
,
Pins
(
"K16"
),
IOStandard
(
"LVCMOS33"
)),
(
"user_btn"
,
2
,
Pins
(
"J16"
),
IOStandard
(
"LVCMOS33"
)),
(
"user_btn"
,
3
,
Pins
(
"H13"
),
IOStandard
(
"LVCMOS33"
)),
(
"clk100"
,
0
,
Pins
(
"R2"
),
IOStandard
(
"SSTL135"
)),
(
"cpu_reset"
,
0
,
Pins
(
"C18"
),
IOStandard
(
"LVCMOS33"
)),
(
"serial"
,
0
,
Subsignal
(
"tx"
,
Pins
(
"R12"
)),
Subsignal
(
"rx"
,
Pins
(
"V12"
)),
IOStandard
(
"LVCMOS33"
)),
(
"spi"
,
0
,
Subsignal
(
"clk"
,
Pins
(
"G16"
)),
Subsignal
(
"cs_n"
,
Pins
(
"H16"
)),
Subsignal
(
"mosi"
,
Pins
(
"H17"
)),
Subsignal
(
"miso"
,
Pins
(
"K14"
)),
IOStandard
(
"LVCMOS33"
)
),
(
"i2c"
,
0
,
Subsignal
(
"scl"
,
Pins
(
"J14"
)),
Subsignal
(
"sda"
,
Pins
(
"J13"
)),
IOStandard
(
"LVCMOS33"
),
),
(
"spiflash4x"
,
0
,
# clock needs to be accessed through STARTUPE2
Subsignal
(
"cs_n"
,
Pins
(
"M13"
)),
Subsignal
(
"clk"
,
Pins
(
"D11"
)),
Subsignal
(
"dq"
,
Pins
(
"K17"
,
"K18"
,
"L14"
,
"M15"
)),
IOStandard
(
"LVCMOS33"
)
),
(
"spiflash"
,
0
,
# clock needs to be accessed through STARTUPE2
Subsignal
(
"cs_n"
,
Pins
(
"M13"
)),
Subsignal
(
"clk"
,
Pins
(
"D11"
)),
Subsignal
(
"mosi"
,
Pins
(
"K17"
)),
Subsignal
(
"miso"
,
Pins
(
"K18"
)),
Subsignal
(
"wp"
,
Pins
(
"L14"
)),
Subsignal
(
"hold"
,
Pins
(
"M15"
)),
IOStandard
(
"LVCMOS33"
)
),
(
"ddram"
,
0
,
Subsignal
(
"a"
,
Pins
(
"U2 R4 V2 V4 T3 R7 V6 T6"
,
"U7 V7 P6 T5 R6 U6"
),
IOStandard
(
"SSTL135"
)),
Subsignal
(
"ba"
,
Pins
(
"V5 T1 U3"
),
IOStandard
(
"SSTL135"
)),
Subsignal
(
"ras_n"
,
Pins
(
"U1"
),
IOStandard
(
"SSTL135"
)),
Subsignal
(
"cas_n"
,
Pins
(
"V3"
),
IOStandard
(
"SSTL135"
)),
Subsignal
(
"we_n"
,
Pins
(
"P7"
),
IOStandard
(
"SSTL135"
)),
Subsignal
(
"cs_n"
,
Pins
(
"R3"
),
IOStandard
(
"SSTL135"
)),
Subsignal
(
"dm"
,
Pins
(
"K4 M3"
),
IOStandard
(
"SSTL135"
)),
Subsignal
(
"dq"
,
Pins
(
"K2 K3 L4 M6 K6 M4 L5 L6"
,
"N4 R1 N1 N5 M2 P1 M1 P2"
),
IOStandard
(
"SSTL135"
),
Misc
(
"IN_TERM=UNTUNED_SPLIT_40"
)),
Subsignal
(
"dqs_p"
,
Pins
(
"K1 N3"
),
IOStandard
(
"DIFF_SSTL135"
),
Misc
(
"IN_TERM=UNTUNED_SPLIT_40"
)),
Subsignal
(
"dqs_n"
,
Pins
(
"L1 N2"
),
IOStandard
(
"DIFF_SSTL135"
),
Misc
(
"IN_TERM=UNTUNED_SPLIT_40"
)),
Subsignal
(
"clk_p"
,
Pins
(
"R5"
),
IOStandard
(
"DIFF_SSTL135"
)),
Subsignal
(
"clk_n"
,
Pins
(
"T4"
),
IOStandard
(
"DIFF_SSTL135"
)),
Subsignal
(
"cke"
,
Pins
(
"T2"
),
IOStandard
(
"SSTL135"
)),
Subsignal
(
"odt"
,
Pins
(
"P5"
),
IOStandard
(
"SSTL135"
)),
Subsignal
(
"reset_n"
,
Pins
(
"J6"
),
IOStandard
(
"SSTL135"
)),
Misc
(
"SLEW=FAST"
),
),
]
# Connectors ---------------------------------------------------------------------------------------
_connectors
=
[
(
"pmoda"
,
"L17 L18 M14 N14 M16 M17 M18 N18"
),
(
"pmodb"
,
"P17 P18 R18 T18 P14 P15 N15 P16"
),
(
"pmodc"
,
"U15 V16 U17 U18 U16 P13 R13 V14"
),
(
"pmodd"
,
"V15 U12 V13 T12 T13 R11 T11 U11"
),
(
"ck_io"
,
{
# Outer Digital Header
"ck_io0"
:
"L13"
,
"ck_io1"
:
"N13"
,
"ck_io2"
:
"L16"
,
"ck_io3"
:
"R14"
,
"ck_io4"
:
"T14"
,
"ck_io5"
:
"R16"
,
"ck_io6"
:
"R17"
,
"ck_io7"
:
"V17"
,
"ck_io8"
:
"R15"
,
"ck_io9"
:
"T15"
,
"ck_io10"
:
"H16"
,
"ck_io11"
:
"H17"
,
"ck_io12"
:
"K14"
,
"ck_io13"
:
"G16"
,
# Inner Digital Header
"ck_io26"
:
"U11"
,
"ck_io27"
:
"T11"
,
"ck_io28"
:
"R11"
,
"ck_io29"
:
"T13"
,
"ck_io30"
:
"T12"
,
"ck_io31"
:
"V13"
,
"ck_io32"
:
"U12"
,
"ck_io33"
:
"V15"
,
"ck_io34"
:
"V14"
,
"ck_io35"
:
"R13"
,
"ck_io36"
:
"P13"
,
"ck_io37"
:
"U16"
,
"ck_io38"
:
"U18"
,
"ck_io39"
:
"U17"
,
"ck_io40"
:
"V16"
,
"ck_io41"
:
"U15"
,
# Outer Analog Header as Digital IO
"ck_a0"
:
"G13"
,
"ck_a1"
:
"B16"
,
"ck_a2"
:
"A16"
,
"ck_a3"
:
"C13"
,
"ck_a4"
:
"C14"
,
"ck_a5"
:
"D18"
,
# Inner Analog Header as Digital IO
"ck_a6"
:
"B14"
,
"ck_a7"
:
"A14"
,
"ck_a8"
:
"D16"
,
"ck_a9"
:
"D17"
,
"ck_a10"
:
"D14"
,
"ck_a11"
:
"D15"
,
}
),
(
"XADC"
,
{
# Outer Analog Header
"vaux0_p"
:
"B13"
,
"vaux0_n"
:
"A13"
,
"vaux1_p"
:
"B15"
,
"vaux1_n"
:
"A15"
,
"vaux9_p"
:
"E12"
,
"vaux9_n"
:
"D12"
,
"vaux2_p"
:
"B17"
,
"vaux2_n"
:
"A17"
,
"vaux10_p"
:
"C17"
,
"vaux10_n"
:
"B18"
,
"vaux11_p"
:
"E16"
,
"vaux11_n"
:
"E17"
,
# Inner Analog Header
"vaux8_p"
:
"B14"
,
"vaux8_n"
:
"A14"
,
"vaux3_p"
:
"D16"
,
"vaux3_n"
:
"D17"
,
}
),
]
# Platform -----------------------------------------------------------------------------------------
class
Platform
(
XilinxPlatform
):
default_clk_name
=
"clk100"
default_clk_period
=
1e9
/
100e6
def
__init__
(
self
,
variant
=
"s7-50"
):
device
=
{
"s7-25"
:
"xc7s25csga324-1"
,
"s7-50"
:
"xc7s50csga324-1"
}[
variant
]
XilinxPlatform
.
__init__
(
self
,
device
,
_io
,
_connectors
,
toolchain
=
"vivado"
)
self
.
toolchain
.
bitstream_commands
=
\
[
"set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"
]
self
.
toolchain
.
additional_commands
=
\
[
"write_cfgmem -force -format bin -interface spix4 -size 16 "
"-loadbit
\"
up 0x0 {build_name}.bit
\"
-file {build_name}.bin"
]
self
.
add_platform_command
(
"set_property INTERNAL_VREF 0.675 [get_iobanks 34]"
)
def
create_programmer
(
self
):
bscan_spi
=
"bscan_spi_xc7s50.bit"
if
"xc7s50"
in
self
.
device
else
"bscan_spi_xc7a25.bit"
return
OpenOCD
(
"openocd_xc7_ft2232.cfg"
,
bscan_spi
)
def
do_finalize
(
self
,
fragment
):
XilinxPlatform
.
do_finalize
(
self
,
fragment
)
self
.
add_period_constraint
(
self
.
lookup_request
(
"clk100"
,
loose
=
True
),
1e9
/
100e6
)
This diff is collapsed.
Click to expand it.
litex_boards/
official/
platforms/avalanche.py
→
litex_boards/platforms/avalanche.py
View file @
a7d6de78
...
@@ -27,41 +27,41 @@ _io = [
...
@@ -27,41 +27,41 @@ _io = [
),
),
(
"spiflash4x"
,
0
,
(
"spiflash4x"
,
0
,
Subsignal
(
"clk"
,
Pins
(
"J1"
)),
Subsignal
(
"clk"
,
Pins
(
"J1"
)),
Subsignal
(
"cs_n"
,
Pins
(
"H1"
)),
Subsignal
(
"cs_n"
,
Pins
(
"H1"
)),
Subsignal
(
"dq"
,
Pins
(
"F2 F1 M7 M8"
)),
Subsignal
(
"dq"
,
Pins
(
"F2 F1 M7 M8"
)),
IOStandard
(
"LVCMOS25"
)
IOStandard
(
"LVCMOS25"
)
),
),
(
"spiflash"
,
0
,
(
"spiflash"
,
0
,
Subsignal
(
"clk"
,
Pins
(
"J1"
)),
Subsignal
(
"clk"
,
Pins
(
"J1"
)),
Subsignal
(
"cs_n"
,
Pins
(
"H1"
)),
Subsignal
(
"cs_n"
,
Pins
(
"H1"
)),
Subsignal
(
"mosi"
,
Pins
(
"F2"
)),
Subsignal
(
"mosi"
,
Pins
(
"F2"
)),
Subsignal
(
"miso"
,
Pins
(
"F1"
)),
Subsignal
(
"miso"
,
Pins
(
"F1"
)),
Subsignal
(
"wp"
,
Pins
(
"M7"
)),
Subsignal
(
"wp"
,
Pins
(
"M7"
)),
Subsignal
(
"hold"
,
Pins
(
"M8"
)),
Subsignal
(
"hold"
,
Pins
(
"M8"
)),
IOStandard
(
"LVCMOS25"
),
IOStandard
(
"LVCMOS25"
),
),
),
(
"ddram"
,
0
,
(
"ddram"
,
0
,
Subsignal
(
"a"
,
Pins
(
Subsignal
(
"a"
,
Pins
(
"U5 U4 V4 W3 V5 W4 Y3 AA3"
,
"U5 U4
V4
W3 V5 W4
Y3 AA3"
,
"Y4 Y5 AA2 AB2 V6 W6 AB3"
),
"Y4 Y5 AA2 AB2 V6 W6 AB3"
),
IOStandard
(
"SSTL15II"
)),
IOStandard
(
"SSTL15II"
)),
Subsignal
(
"ba"
,
Pins
(
"V7 Y6 U7"
),
IOStandard
(
"SSTL15II"
)),
Subsignal
(
"ba"
,
Pins
(
"V7 Y6 U7"
),
IOStandard
(
"SSTL15II"
)),
Subsignal
(
"ras_n"
,
Pins
(
"AA6"
),
IOStandard
(
"SSTL15II"
)),
Subsignal
(
"ras_n"
,
Pins
(
"AA6"
),
IOStandard
(
"SSTL15II"
)),
Subsignal
(
"cas_n"
,
Pins
(
"AA5"
),
IOStandard
(
"SSTL15II"
)),
Subsignal
(
"cas_n"
,
Pins
(
"AA5"
),
IOStandard
(
"SSTL15II"
)),
Subsignal
(
"we_n"
,
Pins
(
"AB5"
),
IOStandard
(
"SSTL15II"
)),
Subsignal
(
"we_n"
,
Pins
(
"AB5"
),
IOStandard
(
"SSTL15II"
)),
Subsignal
(
"cs_n"
,
Pins
(
"W7"
),
IOStandard
(
"SSTL15II"
)),
Subsignal
(
"cs_n"
,
Pins
(
"W7"
),
IOStandard
(
"SSTL15II"
)),
Subsignal
(
"dm"
,
Pins
(
"Y9 R15"
),
IOStandard
(
"SSTL15II"
)),
Subsignal
(
"dm"
,
Pins
(
"Y9 R15"
),
IOStandard
(
"SSTL15II"
)),
Subsignal
(
"dq"
,
Pins
(
Subsignal
(
"dq"
,
Pins
(
"T7 T8 U8 U9 R10 V9 V10 W9"
,
"T7
T8
U8 U9
R10
V9 V10 W9"
,
"V14 U14 R12 T11 U15 T13 U13 T15"
),
"V14 U14 R12 T11 U15 T13 U13 T15"
),
IOStandard
(
"SSTL15II"
)),
IOStandard
(
"SSTL15II"
)),
Subsignal
(
"dqs_p"
,
Pins
(
"T10 R13"
),
IOStandard
(
"SSTL15II"
)),
Subsignal
(
"dqs_p"
,
Pins
(
"T10 R13"
),
IOStandard
(
"SSTL15II"
)),
Subsignal
(
"dqs_n"
,
Pins
(
"U10 T12"
),
IOStandard
(
"SSTL15II"
)),
Subsignal
(
"dqs_n"
,
Pins
(
"U10 T12"
),
IOStandard
(
"SSTL15II"
)),
Subsignal
(
"clk_p"
,
Pins
(
"V2"
),
IOStandard
(
"SSTL15II"
)),
Subsignal
(
"clk_p"
,
Pins
(
"V2"
),
IOStandard
(
"SSTL15II"
)),
Subsignal
(
"clk_n"
,
Pins
(
"W2"
),
IOStandard
(
"SSTL15II"
)),
Subsignal
(
"clk_n"
,
Pins
(
"W2"
),
IOStandard
(
"SSTL15II"
)),
Subsignal
(
"cke"
,
Pins
(
"W8"
),
IOStandard
(
"SSTL15II"
)),
Subsignal
(
"cke"
,
Pins
(
"W8"
),
IOStandard
(
"SSTL15II"
)),
Subsignal
(
"odt"
,
Pins
(
"AA7"
),
IOStandard
(
"SSTL15II"
)),
Subsignal
(
"odt"
,
Pins
(
"AA7"
),
IOStandard
(
"SSTL15II"
)),
Subsignal
(
"reset_n"
,
Pins
(
"AB7"
),
IOStandard
(
"SSTL15II"
)),
Subsignal
(
"reset_n"
,
Pins
(
"AB7"
),
IOStandard
(
"SSTL15II"
)),
),
),
...
@@ -72,13 +72,13 @@ _io = [
...
@@ -72,13 +72,13 @@ _io = [
IOStandard
(
"LVCMOS25"
)
IOStandard
(
"LVCMOS25"
)
),
),
(
"eth"
,
0
,
(
"eth"
,
0
,
Subsignal
(
"rst_n"
,
Pins
(
"L8"
),
IOStandard
(
"LVCMOS33"
)),
Subsignal
(
"rst_n"
,
Pins
(
"L8"
),
IOStandard
(
"LVCMOS33"
)),
Subsignal
(
"int_n"
,
Pins
(
"J4"
)),
Subsignal
(
"int_n"
,
Pins
(
"J4"
)),
Subsignal
(
"mdio"
,
Pins
(
"H2"
)),
Subsignal
(
"mdio"
,
Pins
(
"H2"
)),
Subsignal
(
"mdc"
,
Pins
(
"J2"
)),
Subsignal
(
"mdc"
,
Pins
(
"J2"
)),
Subsignal
(
"rx_ctl"
,
Pins
(
"K5"
)),
Subsignal
(
"rx_ctl"
,
Pins
(
"K5"
)),
Subsignal
(
"rx_data"
,
Pins
(
"J9 K1 K6 K4"
)),
Subsignal
(
"rx_data"
,
Pins
(
"J9 K1 K6 K4"
)),
Subsignal
(
"tx_ctl"
,
Pins
(
"L5"
)),
Subsignal
(
"tx_ctl"
,
Pins
(
"L5"
)),
Subsignal
(
"tx_data"
,
Pins
(
"K8 L1 L2 L3"
)),
Subsignal
(
"tx_data"
,
Pins
(
"K8 L1 L2 L3"
)),
IOStandard
(
"LVCMOS25"
)
IOStandard
(
"LVCMOS25"
)
),
),
...
@@ -87,8 +87,13 @@ _io = [
...
@@ -87,8 +87,13 @@ _io = [
# Platform -----------------------------------------------------------------------------------------
# Platform -----------------------------------------------------------------------------------------
class
Platform
(
MicrosemiPlatform
):
class
Platform
(
MicrosemiPlatform
):
default_clk_name
=
"clk50"
default_clk_name
=
"clk50"
default_clk_period
=
1e9
/
50e6
default_clk_period
=
1e9
/
50e6
def
__init__
(
self
):
def
__init__
(
self
):
MicrosemiPlatform
.
__init__
(
self
,
"MPF300TS_ES-FCG484-1"
,
_io
)
MicrosemiPlatform
.
__init__
(
self
,
"MPF300TS_ES-FCG484-1"
,
_io
)
def
do_finalize
(
self
,
fragment
):
MicrosemiPlatform
.
do_finalize
(
self
,
fragment
)
self
.
add_period_constraint
(
self
.
lookup_request
(
"clk50"
,
0
,
loose
=
True
),
1e9
/
50e6
)
self
.
add_period_constraint
(
self
.
lookup_request
(
"clk50"
,
1
,
loose
=
True
),
1e9
/
50e6
)
This diff is collapsed.
Click to expand it.
litex_boards/
partner/
platforms/c10lprefkit.py
→
litex_boards/platforms/c10lprefkit.py
View file @
a7d6de78
...
@@ -9,7 +9,7 @@ from litex.build.altera.programmer import USBBlaster
...
@@ -9,7 +9,7 @@ from litex.build.altera.programmer import USBBlaster
# IOs ----------------------------------------------------------------------------------------------
# IOs ----------------------------------------------------------------------------------------------
_io
=
[
_io
=
[
(
"clk12"
,
0
,
Pins
(
"G21"
),
IOStandard
(
"3.3-V LVTTL"
)),
(
"clk12"
,
0
,
Pins
(
"G21"
),
IOStandard
(
"3.3-V LVTTL"
)),
(
"clk25"
,
0
,
Pins
(
"AA12"
),
IOStandard
(
"3.3-V LVTTL"
)),
(
"clk25"
,
0
,
Pins
(
"AA12"
),
IOStandard
(
"3.3-V LVTTL"
)),
(
"user_led"
,
0
,
Pins
(
"C18"
),
IOStandard
(
"3.3-V LVTTL"
)),
(
"user_led"
,
0
,
Pins
(
"C18"
),
IOStandard
(
"3.3-V LVTTL"
)),
...
@@ -35,17 +35,17 @@ _io = [
...
@@ -35,17 +35,17 @@ _io = [
(
"sdram_clock"
,
0
,
Pins
(
"AA3"
),
IOStandard
(
"3.3-V LVTTL"
)),
(
"sdram_clock"
,
0
,
Pins
(
"AA3"
),
IOStandard
(
"3.3-V LVTTL"
)),
(
"sdram"
,
0
,
(
"sdram"
,
0
,
Subsignal
(
"a"
,
Pins
(
Subsignal
(
"a"
,
Pins
(
"V5 Y3 W6 Y4 AB5 AB6 AA6 AA7"
,
"V5
Y3 W6
Y4 AB5 AB6 AA6 AA7"
,
"AB7 AA5 V6 AA8 AB8"
)),
"AB7 AA5 V6 AA8 AB8"
)),
Subsignal
(
"ba"
,
Pins
(
"Y6 V7"
)),
Subsignal
(
"ba"
,
Pins
(
"Y6 V7"
)),
Subsignal
(
"cs_n"
,
Pins
(
"W7"
)),
Subsignal
(
"cs_n"
,
Pins
(
"W7"
)),
Subsignal
(
"cke"
,
Pins
(
"AA4"
)),
Subsignal
(
"cke"
,
Pins
(
"AA4"
)),
Subsignal
(
"ras_n"
,
Pins
(
"V8"
)),
Subsignal
(
"ras_n"
,
Pins
(
"V8"
)),
Subsignal
(
"cas_n"
,
Pins
(
"Y7"
)),
Subsignal
(
"cas_n"
,
Pins
(
"Y7"
)),
Subsignal
(
"we_n"
,
Pins
(
"W8"
)),
Subsignal
(
"we_n"
,
Pins
(
"W8"
)),
Subsignal
(
"dq"
,
Pins
(
Subsignal
(
"dq"
,
Pins
(
"AB16 Y17 AA16 AA19 AB18 AA20 AB19 AB20"
,
"AB16 Y17 AA16 AA19 AB18 AA20 AB19 AB20"
,
"Y13 Y15 AA13 AB15 AB13 AA15 AA14 AB14"
)),
"Y13
Y15 AA13 AB15 AB13 AA15 AA14 AB14"
)),
Subsignal
(
"dm"
,
Pins
(
"Y14 W13"
)),
Subsignal
(
"dm"
,
Pins
(
"Y14 W13"
)),
IOStandard
(
"3.3-V LVTTL"
)
IOStandard
(
"3.3-V LVTTL"
)
),
),
...
@@ -59,11 +59,11 @@ _io = [
...
@@ -59,11 +59,11 @@ _io = [
),
),
(
"hyperram"
,
0
,
(
"hyperram"
,
0
,
Subsignal
(
"clk"
,
Pins
(
"T16"
)),
Subsignal
(
"clk"
,
Pins
(
"T16"
)),
Subsignal
(
"rst_n"
,
Pins
(
"U12"
)),
Subsignal
(
"rst_n"
,
Pins
(
"U12"
)),
Subsignal
(
"dq"
,
Pins
(
"T15 W17 U14 R15 R14 V16 U16 U17"
)),
Subsignal
(
"dq"
,
Pins
(
"T15 W17 U14 R15 R14 V16 U16 U17"
)),
Subsignal
(
"cs_n"
,
Pins
(
"V13"
)),
Subsignal
(
"cs_n"
,
Pins
(
"V13"
)),
Subsignal
(
"rwds"
,
Pins
(
"U13"
)),
Subsignal
(
"rwds"
,
Pins
(
"U13"
)),
IOStandard
(
"3.3-V LVTTL"
)
IOStandard
(
"3.3-V LVTTL"
)
),
),
...
@@ -78,16 +78,16 @@ _io = [
...
@@ -78,16 +78,16 @@ _io = [
IOStandard
(
"3.3-V LVTTL"
),
IOStandard
(
"3.3-V LVTTL"
),
),
),
(
"eth"
,
0
,
(
"eth"
,
0
,
Subsignal
(
"rst_n"
,
Pins
(
"R19"
)),
Subsignal
(
"rst_n"
,
Pins
(
"R19"
)),
Subsignal
(
"mdio"
,
Pins
(
"AA21"
)),
Subsignal
(
"mdio"
,
Pins
(
"AA21"
)),
Subsignal
(
"mdc"
,
Pins
(
"AA22"
)),
Subsignal
(
"mdc"
,
Pins
(
"AA22"
)),
Subsignal
(
"rx_dv"
,
Pins
(
"W21"
)),
Subsignal
(
"rx_dv"
,
Pins
(
"W21"
)),
Subsignal
(
"rx_er"
,
Pins
(
"V21"
)),
Subsignal
(
"rx_er"
,
Pins
(
"V21"
)),
Subsignal
(
"rx_data"
,
Pins
(
"W22 W20 Y21 Y22"
)),
Subsignal
(
"rx_data"
,
Pins
(
"W22 W20 Y21 Y22"
)),
Subsignal
(
"tx_en"
,
Pins
(
"T18"
)),
Subsignal
(
"tx_en"
,
Pins
(
"T18"
)),
Subsignal
(
"tx_data"
,
Pins
(
"T17 U20 U19 T20"
)),
Subsignal
(
"tx_data"
,
Pins
(
"T17 U20 U19 T20"
)),
Subsignal
(
"col"
,
Pins
(
"T19"
)),
Subsignal
(
"col"
,
Pins
(
"T19"
)),
Subsignal
(
"crs"
,
Pins
(
"R20"
)),
Subsignal
(
"crs"
,
Pins
(
"R20"
)),
IOStandard
(
"3.3-V LVTTL"
),
IOStandard
(
"3.3-V LVTTL"
),
),
),
...
@@ -97,16 +97,16 @@ _io = [
...
@@ -97,16 +97,16 @@ _io = [
IOStandard
(
"3.3-V LVTTL"
),
IOStandard
(
"3.3-V LVTTL"
),
),
),
(
"eth"
,
1
,
(
"eth"
,
1
,
Subsignal
(
"rst_n"
,
Pins
(
"M21"
)),
Subsignal
(
"rst_n"
,
Pins
(
"M21"
)),
Subsignal
(
"mdio"
,
Pins
(
"N20"
)),
Subsignal
(
"mdio"
,
Pins
(
"N20"
)),
Subsignal
(
"mdc"
,
Pins
(
"N18"
)),
Subsignal
(
"mdc"
,
Pins
(
"N18"
)),
Subsignal
(
"rx_dv"
,
Pins
(
"R18"
)),
Subsignal
(
"rx_dv"
,
Pins
(
"R18"
)),
Subsignal
(
"rx_er"
,
Pins
(
"P17"
)),
Subsignal
(
"rx_er"
,
Pins
(
"P17"
)),
Subsignal
(
"rx_data"
,
Pins
(
"M20 M19 M16 N19"
)),
Subsignal
(
"rx_data"
,
Pins
(
"M20 M19 M16 N19"
)),
Subsignal
(
"tx_en"
,
Pins
(
"R22"
)),
Subsignal
(
"tx_en"
,
Pins
(
"R22"
)),
Subsignal
(
"tx_data"
,
Pins
(
"R21 N21 M22 N22"
)),
Subsignal
(
"tx_data"
,
Pins
(
"R21 N21 M22 N22"
)),
Subsignal
(
"col"
,
Pins
(
"P21"
)),
Subsignal
(
"col"
,
Pins
(
"P21"
)),
Subsignal
(
"crs"
,
Pins
(
"P22"
)),
Subsignal
(
"crs"
,
Pins
(
"P22"
)),
IOStandard
(
"3.3-V LVTTL"
),
IOStandard
(
"3.3-V LVTTL"
),
),
),
]
]
...
@@ -114,7 +114,7 @@ _io = [
...
@@ -114,7 +114,7 @@ _io = [
# Platform -----------------------------------------------------------------------------------------
# Platform -----------------------------------------------------------------------------------------
class
Platform
(
AlteraPlatform
):
class
Platform
(
AlteraPlatform
):
default_clk_name
=
"clk12"
default_clk_name
=
"clk12"
default_clk_period
=
1e9
/
12e6
default_clk_period
=
1e9
/
12e6
def
__init__
(
self
):
def
__init__
(
self
):
...
@@ -122,3 +122,8 @@ class Platform(AlteraPlatform):
...
@@ -122,3 +122,8 @@ class Platform(AlteraPlatform):
def
create_programmer
(
self
):
def
create_programmer
(
self
):
return
USBBlaster
()
return
USBBlaster
()
def
do_finalize
(
self
,
fragment
):
AlteraPlatform
.
do_finalize
(
self
,
fragment
)
self
.
add_period_constraint
(
self
.
lookup_request
(
"clk12"
,
loose
=
True
),
1e9
/
12e6
)
self
.
add_period_constraint
(
self
.
lookup_request
(
"clk25"
,
loose
=
True
),
1e9
/
25e6
)
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