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Timothy Pearson
litex-boards
Commits
84468c2a
Commit
84468c2a
authored
4 years ago
by
Florent Kermarrec
Browse files
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Plain Diff
targets/CRG: platforms are now automatically constraining the input clocks.
parent
1f88a9d5
Changes
19
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19 changed files
with
0 additions
and
21 deletions
+0
-21
litex_boards/targets/aller.py
litex_boards/targets/aller.py
+0
-1
litex_boards/targets/c10lprefkit.py
litex_boards/targets/c10lprefkit.py
+0
-1
litex_boards/targets/camlink_4k.py
litex_boards/targets/camlink_4k.py
+0
-1
litex_boards/targets/colorlight_5a_75b.py
litex_boards/targets/colorlight_5a_75b.py
+0
-1
litex_boards/targets/de0nano.py
litex_boards/targets/de0nano.py
+0
-1
litex_boards/targets/de10lite.py
litex_boards/targets/de10lite.py
+0
-1
litex_boards/targets/de10nano.py
litex_boards/targets/de10nano.py
+0
-1
litex_boards/targets/de1soc.py
litex_boards/targets/de1soc.py
+0
-1
litex_boards/targets/de2_115.py
litex_boards/targets/de2_115.py
+0
-1
litex_boards/targets/ecp5_evn.py
litex_boards/targets/ecp5_evn.py
+0
-1
litex_boards/targets/ecpix5.py
litex_boards/targets/ecpix5.py
+0
-1
litex_boards/targets/hadbadge.py
litex_boards/targets/hadbadge.py
+0
-1
litex_boards/targets/linsn_rv901t.py
litex_boards/targets/linsn_rv901t.py
+0
-3
litex_boards/targets/nereid.py
litex_boards/targets/nereid.py
+0
-1
litex_boards/targets/orangecrab.py
litex_boards/targets/orangecrab.py
+0
-1
litex_boards/targets/tagus.py
litex_boards/targets/tagus.py
+0
-1
litex_boards/targets/trellisboard.py
litex_boards/targets/trellisboard.py
+0
-1
litex_boards/targets/ulx3s.py
litex_boards/targets/ulx3s.py
+0
-1
litex_boards/targets/versa_ecp5.py
litex_boards/targets/versa_ecp5.py
+0
-1
No files found.
litex_boards/targets/aller.py
View file @
84468c2a
...
@@ -48,7 +48,6 @@ class CRG(Module, AutoCSR):
...
@@ -48,7 +48,6 @@ class CRG(Module, AutoCSR):
# Clk/Rst
# Clk/Rst
clk100
=
platform
.
request
(
"clk100"
)
clk100
=
platform
.
request
(
"clk100"
)
platform
.
add_period_constraint
(
clk100
,
1e9
/
100e6
)
# Delay software reset by 10us to ensure write has been acked on PCIe.
# Delay software reset by 10us to ensure write has been acked on PCIe.
rst_delay
=
WaitTimer
(
int
(
10e-6
*
sys_clk_freq
))
rst_delay
=
WaitTimer
(
int
(
10e-6
*
sys_clk_freq
))
...
...
This diff is collapsed.
Click to expand it.
litex_boards/targets/c10lprefkit.py
View file @
84468c2a
...
@@ -34,7 +34,6 @@ class _CRG(Module):
...
@@ -34,7 +34,6 @@ class _CRG(Module):
# Clk / Rst
# Clk / Rst
clk12
=
platform
.
request
(
"clk12"
)
clk12
=
platform
.
request
(
"clk12"
)
platform
.
add_period_constraint
(
clk12
,
1e9
/
12e6
)
# PLL
# PLL
self
.
submodules
.
pll
=
pll
=
Cyclone10LPPLL
(
speedgrade
=
"-A7"
)
self
.
submodules
.
pll
=
pll
=
Cyclone10LPPLL
(
speedgrade
=
"-A7"
)
...
...
This diff is collapsed.
Click to expand it.
litex_boards/targets/camlink_4k.py
View file @
84468c2a
...
@@ -37,7 +37,6 @@ class _CRG(Module):
...
@@ -37,7 +37,6 @@ class _CRG(Module):
# clk / rst
# clk / rst
clk27
=
platform
.
request
(
"clk27"
)
clk27
=
platform
.
request
(
"clk27"
)
platform
.
add_period_constraint
(
clk27
,
1e9
/
27e6
)
# power on reset
# power on reset
por_count
=
Signal
(
16
,
reset
=
2
**
16
-
1
)
por_count
=
Signal
(
16
,
reset
=
2
**
16
-
1
)
...
...
This diff is collapsed.
Click to expand it.
litex_boards/targets/colorlight_5a_75b.py
View file @
84468c2a
...
@@ -67,7 +67,6 @@ class _CRG(Module):
...
@@ -67,7 +67,6 @@ class _CRG(Module):
# Clk / Rst
# Clk / Rst
clk25
=
platform
.
request
(
"clk25"
)
clk25
=
platform
.
request
(
"clk25"
)
rst_n
=
1
if
not
with_rst
else
platform
.
request
(
"user_btn_n"
,
0
)
rst_n
=
1
if
not
with_rst
else
platform
.
request
(
"user_btn_n"
,
0
)
platform
.
add_period_constraint
(
clk25
,
1e9
/
25e6
)
# PLL
# PLL
self
.
submodules
.
pll
=
pll
=
ECP5PLL
()
self
.
submodules
.
pll
=
pll
=
ECP5PLL
()
...
...
This diff is collapsed.
Click to expand it.
litex_boards/targets/de0nano.py
View file @
84468c2a
...
@@ -31,7 +31,6 @@ class _CRG(Module):
...
@@ -31,7 +31,6 @@ class _CRG(Module):
# Clk / Rst
# Clk / Rst
clk50
=
platform
.
request
(
"clk50"
)
clk50
=
platform
.
request
(
"clk50"
)
platform
.
add_period_constraint
(
clk50
,
1e9
/
50e6
)
# PLL
# PLL
self
.
submodules
.
pll
=
pll
=
CycloneIVPLL
(
speedgrade
=
"-6"
)
self
.
submodules
.
pll
=
pll
=
CycloneIVPLL
(
speedgrade
=
"-6"
)
...
...
This diff is collapsed.
Click to expand it.
litex_boards/targets/de10lite.py
View file @
84468c2a
...
@@ -34,7 +34,6 @@ class _CRG(Module):
...
@@ -34,7 +34,6 @@ class _CRG(Module):
# Clk / Rst
# Clk / Rst
clk50
=
platform
.
request
(
"clk50"
)
clk50
=
platform
.
request
(
"clk50"
)
platform
.
add_period_constraint
(
clk50
,
1e9
/
50e6
)
# PLL
# PLL
self
.
submodules
.
pll
=
pll
=
Max10PLL
(
speedgrade
=
"-7"
)
self
.
submodules
.
pll
=
pll
=
Max10PLL
(
speedgrade
=
"-7"
)
...
...
This diff is collapsed.
Click to expand it.
litex_boards/targets/de10nano.py
View file @
84468c2a
...
@@ -31,7 +31,6 @@ class _CRG(Module):
...
@@ -31,7 +31,6 @@ class _CRG(Module):
# Clk / Rst
# Clk / Rst
clk50
=
platform
.
request
(
"clk50"
)
clk50
=
platform
.
request
(
"clk50"
)
platform
.
add_period_constraint
(
clk50
,
1e9
/
50e6
)
# PLL
# PLL
self
.
submodules
.
pll
=
pll
=
CycloneVPLL
(
speedgrade
=
"-I7"
)
self
.
submodules
.
pll
=
pll
=
CycloneVPLL
(
speedgrade
=
"-I7"
)
...
...
This diff is collapsed.
Click to expand it.
litex_boards/targets/de1soc.py
View file @
84468c2a
...
@@ -31,7 +31,6 @@ class _CRG(Module):
...
@@ -31,7 +31,6 @@ class _CRG(Module):
# Clk / Rst
# Clk / Rst
clk50
=
platform
.
request
(
"clk50"
)
clk50
=
platform
.
request
(
"clk50"
)
platform
.
add_period_constraint
(
clk50
,
1e9
/
50e6
)
# PLL
# PLL
self
.
submodules
.
pll
=
pll
=
CycloneVPLL
(
speedgrade
=
"-C6"
)
self
.
submodules
.
pll
=
pll
=
CycloneVPLL
(
speedgrade
=
"-C6"
)
...
...
This diff is collapsed.
Click to expand it.
litex_boards/targets/de2_115.py
View file @
84468c2a
...
@@ -31,7 +31,6 @@ class _CRG(Module):
...
@@ -31,7 +31,6 @@ class _CRG(Module):
# Clk / Rst
# Clk / Rst
clk50
=
platform
.
request
(
"clk50"
)
clk50
=
platform
.
request
(
"clk50"
)
platform
.
add_period_constraint
(
clk50
,
1e9
/
50e6
)
# PLL
# PLL
self
.
submodules
.
pll
=
pll
=
CycloneIVPLL
(
speedgrade
=
"-7"
)
self
.
submodules
.
pll
=
pll
=
CycloneIVPLL
(
speedgrade
=
"-7"
)
...
...
This diff is collapsed.
Click to expand it.
litex_boards/targets/ecp5_evn.py
View file @
84468c2a
...
@@ -25,7 +25,6 @@ class _CRG(Module):
...
@@ -25,7 +25,6 @@ class _CRG(Module):
# clk / rst
# clk / rst
clk
=
clk12
=
platform
.
request
(
"clk12"
)
clk
=
clk12
=
platform
.
request
(
"clk12"
)
rst_n
=
platform
.
request
(
"rst_n"
)
rst_n
=
platform
.
request
(
"rst_n"
)
platform
.
add_period_constraint
(
clk12
,
1e9
/
12e6
)
if
x5_clk_freq
is
not
None
:
if
x5_clk_freq
is
not
None
:
clk
=
clk50
=
platform
.
request
(
"ext_clk50"
)
clk
=
clk50
=
platform
.
request
(
"ext_clk50"
)
self
.
comb
+=
platform
.
request
(
"ext_clk50_en"
).
eq
(
1
)
self
.
comb
+=
platform
.
request
(
"ext_clk50_en"
).
eq
(
1
)
...
...
This diff is collapsed.
Click to expand it.
litex_boards/targets/ecpix5.py
View file @
84468c2a
...
@@ -39,7 +39,6 @@ class _CRG(Module):
...
@@ -39,7 +39,6 @@ class _CRG(Module):
# Clk / Rst
# Clk / Rst
clk100
=
platform
.
request
(
"clk100"
)
clk100
=
platform
.
request
(
"clk100"
)
rst_n
=
platform
.
request
(
"rst_n"
)
rst_n
=
platform
.
request
(
"rst_n"
)
platform
.
add_period_constraint
(
clk100
,
1e9
/
100e6
)
# Power on reset
# Power on reset
por_count
=
Signal
(
16
,
reset
=
2
**
16
-
1
)
por_count
=
Signal
(
16
,
reset
=
2
**
16
-
1
)
...
...
This diff is collapsed.
Click to expand it.
litex_boards/targets/hadbadge.py
View file @
84468c2a
...
@@ -38,7 +38,6 @@ class _CRG(Module):
...
@@ -38,7 +38,6 @@ class _CRG(Module):
# Clk / Rst
# Clk / Rst
clk8
=
platform
.
request
(
"clk8"
)
clk8
=
platform
.
request
(
"clk8"
)
platform
.
add_period_constraint
(
clk8
,
1e9
/
8e6
)
# PLL
# PLL
self
.
submodules
.
pll
=
pll
=
ECP5PLL
()
self
.
submodules
.
pll
=
pll
=
ECP5PLL
()
...
...
This diff is collapsed.
Click to expand it.
litex_boards/targets/linsn_rv901t.py
View file @
84468c2a
...
@@ -32,7 +32,6 @@ class _CRG(Module):
...
@@ -32,7 +32,6 @@ class _CRG(Module):
# # #
# # #
clk25
=
platform
.
request
(
"clk25"
)
clk25
=
platform
.
request
(
"clk25"
)
platform
.
add_period_constraint
(
clk25
,
1e9
/
25e6
)
self
.
submodules
.
pll
=
pll
=
S6PLL
(
speedgrade
=-
2
)
self
.
submodules
.
pll
=
pll
=
S6PLL
(
speedgrade
=-
2
)
pll
.
register_clkin
(
clk25
,
25e6
)
pll
.
register_clkin
(
clk25
,
25e6
)
...
@@ -96,8 +95,6 @@ class EthernetSoC(BaseSoC):
...
@@ -96,8 +95,6 @@ class EthernetSoC(BaseSoC):
self
.
add_csr
(
"ethmac"
)
self
.
add_csr
(
"ethmac"
)
self
.
add_interrupt
(
"ethmac"
)
self
.
add_interrupt
(
"ethmac"
)
# timing constraints
# timing constraints
self
.
platform
.
add_period_constraint
(
self
.
ethphy
.
crg
.
cd_eth_rx
.
clk
,
1e9
/
125e6
)
self
.
platform
.
add_period_constraint
(
self
.
ethphy
.
crg
.
cd_eth_tx
.
clk
,
1e9
/
125e6
)
self
.
platform
.
add_false_path_constraints
(
self
.
platform
.
add_false_path_constraints
(
self
.
crg
.
cd_sys
.
clk
,
self
.
crg
.
cd_sys
.
clk
,
self
.
ethphy
.
crg
.
cd_eth_rx
.
clk
,
self
.
ethphy
.
crg
.
cd_eth_rx
.
clk
,
...
...
This diff is collapsed.
Click to expand it.
litex_boards/targets/nereid.py
View file @
84468c2a
...
@@ -47,7 +47,6 @@ class CRG(Module, AutoCSR):
...
@@ -47,7 +47,6 @@ class CRG(Module, AutoCSR):
# Clk/Rst
# Clk/Rst
clk100
=
platform
.
request
(
"clk100"
)
clk100
=
platform
.
request
(
"clk100"
)
platform
.
add_period_constraint
(
clk100
,
1e9
/
100e6
)
# Delay software reset by 10us to ensure write has been acked on PCIe.
# Delay software reset by 10us to ensure write has been acked on PCIe.
rst_delay
=
WaitTimer
(
int
(
10e-6
*
sys_clk_freq
))
rst_delay
=
WaitTimer
(
int
(
10e-6
*
sys_clk_freq
))
...
...
This diff is collapsed.
Click to expand it.
litex_boards/targets/orangecrab.py
View file @
84468c2a
...
@@ -38,7 +38,6 @@ class _CRG(Module):
...
@@ -38,7 +38,6 @@ class _CRG(Module):
# Clk / Rst
# Clk / Rst
clk48
=
platform
.
request
(
"clk48"
)
clk48
=
platform
.
request
(
"clk48"
)
platform
.
add_period_constraint
(
clk48
,
1e9
/
48e6
)
# Power on reset
# Power on reset
por_count
=
Signal
(
16
,
reset
=
2
**
16
-
1
)
por_count
=
Signal
(
16
,
reset
=
2
**
16
-
1
)
...
...
This diff is collapsed.
Click to expand it.
litex_boards/targets/tagus.py
View file @
84468c2a
...
@@ -46,7 +46,6 @@ class CRG(Module, AutoCSR):
...
@@ -46,7 +46,6 @@ class CRG(Module, AutoCSR):
# Clk/Rst
# Clk/Rst
clk100
=
platform
.
request
(
"clk100"
)
clk100
=
platform
.
request
(
"clk100"
)
platform
.
add_period_constraint
(
clk100
,
1e9
/
100e6
)
# Delay software reset by 10us to ensure write has been acked on PCIe.
# Delay software reset by 10us to ensure write has been acked on PCIe.
rst_delay
=
WaitTimer
(
int
(
10e-6
*
sys_clk_freq
))
rst_delay
=
WaitTimer
(
int
(
10e-6
*
sys_clk_freq
))
...
...
This diff is collapsed.
Click to expand it.
litex_boards/targets/trellisboard.py
View file @
84468c2a
...
@@ -39,7 +39,6 @@ class _CRG(Module):
...
@@ -39,7 +39,6 @@ class _CRG(Module):
# Clk / Rst
# Clk / Rst
clk12
=
platform
.
request
(
"clk12"
)
clk12
=
platform
.
request
(
"clk12"
)
rst
=
platform
.
request
(
"user_btn"
,
0
)
rst
=
platform
.
request
(
"user_btn"
,
0
)
platform
.
add_period_constraint
(
clk12
,
1e9
/
12e6
)
# Power on reset
# Power on reset
por_count
=
Signal
(
16
,
reset
=
2
**
16
-
1
)
por_count
=
Signal
(
16
,
reset
=
2
**
16
-
1
)
...
...
This diff is collapsed.
Click to expand it.
litex_boards/targets/ulx3s.py
View file @
84468c2a
...
@@ -36,7 +36,6 @@ class _CRG(Module):
...
@@ -36,7 +36,6 @@ class _CRG(Module):
# Clk / Rst
# Clk / Rst
clk25
=
platform
.
request
(
"clk25"
)
clk25
=
platform
.
request
(
"clk25"
)
rst
=
platform
.
request
(
"rst"
)
rst
=
platform
.
request
(
"rst"
)
platform
.
add_period_constraint
(
clk25
,
1e9
/
25e6
)
# PLL
# PLL
self
.
submodules
.
pll
=
pll
=
ECP5PLL
()
self
.
submodules
.
pll
=
pll
=
ECP5PLL
()
...
...
This diff is collapsed.
Click to expand it.
litex_boards/targets/versa_ecp5.py
View file @
84468c2a
...
@@ -40,7 +40,6 @@ class _CRG(Module):
...
@@ -40,7 +40,6 @@ class _CRG(Module):
# Clk / Rst
# Clk / Rst
clk100
=
platform
.
request
(
"clk100"
)
clk100
=
platform
.
request
(
"clk100"
)
rst_n
=
platform
.
request
(
"rst_n"
)
rst_n
=
platform
.
request
(
"rst_n"
)
platform
.
add_period_constraint
(
clk100
,
1e9
/
100e6
)
# Power on reset
# Power on reset
por_count
=
Signal
(
16
,
reset
=
2
**
16
-
1
)
por_count
=
Signal
(
16
,
reset
=
2
**
16
-
1
)
...
...
This diff is collapsed.
Click to expand it.
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