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Timothy Pearson
litex-boards
Commits
82d73b83
Commit
82d73b83
authored
5 years ago
by
Florent Kermarrec
Browse files
Options
Download
Plain Diff
Merge branch 'master' of
http://github.com/litex-hub/litex-boards
parents
debafd7c
1fdaf5db
Changes
23
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20 changed files
with
608 additions
and
22 deletions
+608
-22
.gitignore
.gitignore
+3
-0
.travis.yml
.travis.yml
+18
-0
litex_boards/community/platforms/de10lite.py
litex_boards/community/platforms/de10lite.py
+3
-0
litex_boards/community/platforms/de1soc.py
litex_boards/community/platforms/de1soc.py
+2
-3
litex_boards/community/platforms/de2_115.py
litex_boards/community/platforms/de2_115.py
+2
-3
litex_boards/community/platforms/sp605.py
litex_boards/community/platforms/sp605.py
+1
-0
litex_boards/community/platforms/trellisboard.py
litex_boards/community/platforms/trellisboard.py
+216
-0
litex_boards/community/targets/ac701.py
litex_boards/community/targets/ac701.py
+5
-1
litex_boards/community/targets/de10lite.py
litex_boards/community/targets/de10lite.py
+3
-0
litex_boards/community/targets/de1soc.py
litex_boards/community/targets/de1soc.py
+3
-7
litex_boards/community/targets/de2_115.py
litex_boards/community/targets/de2_115.py
+3
-7
litex_boards/community/targets/trellisboard.py
litex_boards/community/targets/trellisboard.py
+146
-0
litex_boards/official/targets/simple.py
litex_boards/official/targets/simple.py
+77
-0
litex_boards/partner/__init__.py
litex_boards/partner/__init__.py
+0
-0
litex_boards/partner/platforms/__init__.py
litex_boards/partner/platforms/__init__.py
+0
-0
litex_boards/partner/platforms/fomu_evt.py
litex_boards/partner/platforms/fomu_evt.py
+5
-1
litex_boards/partner/platforms/fomu_hacker.py
litex_boards/partner/platforms/fomu_hacker.py
+3
-0
litex_boards/partner/platforms/fomu_pvt.py
litex_boards/partner/platforms/fomu_pvt.py
+3
-0
litex_boards/partner/targets/__init__.py
litex_boards/partner/targets/__init__.py
+0
-0
litex_boards/partner/targets/fomu.py
litex_boards/partner/targets/fomu.py
+115
-0
No files found.
.gitignore
0 → 100644
View file @
82d73b83
# Ignore Python temporary files
*.pyc
__pycache__
\ No newline at end of file
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.travis.yml
0 → 100644
View file @
82d73b83
language
:
python
dist
:
Xenial
python
:
"
3.6"
install
:
# Get Migen / LiteX / Cores
-
wget https://raw.githubusercontent.com/enjoy-digital/litex/master/litex_setup.py
-
python3 litex_setup.py init install
# Install LiteX-Boards
-
python3 setup.py develop
before_script
:
# Get RISC-V toolchain
-
wget https://static.dev.sifive.com/dev-tools/riscv64-unknown-elf-gcc-8.1.0-2019.01.0-x86_64-linux-ubuntu14.tar.gz
-
tar -xvf riscv64-unknown-elf-gcc-8.1.0-2019.01.0-x86_64-linux-ubuntu14.tar.gz
-
export PATH=$PATH:$PWD/riscv64-unknown-elf-gcc-8.1.0-2019.01.0-x86_64-linux-ubuntu14/bin/
script
:
python setup.py test
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litex_boards/community/platforms/de10lite.py
View file @
82d73b83
# This file is Copyright (c) 2019 msloniewski <marcin.sloniewski@gmail.com>
# License: BSD
from
litex.build.generic_platform
import
*
from
litex.build.altera
import
AlteraPlatform
from
litex.build.altera.programmer
import
USBBlaster
...
...
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litex_boards/community/platforms/de1soc.py
View file @
82d73b83
# SPDX-License-Identifier: BSD-2-Clause
#
# Copyright (c) 2019 Antony Pavlov <antonynpavlov@gmail.com>
# This file is Copyright (c) 2019 Antony Pavlov <antonynpavlov@gmail.com>
# License: BSD
from
litex.build.generic_platform
import
*
from
litex.build.altera
import
AlteraPlatform
...
...
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litex_boards/community/platforms/de2_115.py
View file @
82d73b83
# SPDX-License-Identifier: BSD-2-Clause
#
# Copyright (c) 2019 Antony Pavlov <antonynpavlov@gmail.com>
# This file is Copyright (c) 2019 Antony Pavlov <antonynpavlov@gmail.com>
# License: BSD
from
litex.build.generic_platform
import
*
from
litex.build.altera
import
AlteraPlatform
...
...
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Click to expand it.
litex_boards/community/platforms/sp605.py
View file @
82d73b83
# This file is Copyright (c) 2019 Michael Betz <michibetz@gmail.com>
# License: BSD
from
litex.build.generic_platform
import
*
from
litex.build.xilinx
import
XilinxPlatform
,
iMPACT
...
...
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litex_boards/community/platforms/trellisboard.py
0 → 100644
View file @
82d73b83
# This file is Copyright (c) 2019 David Shah <dave@ds0.me>
# License: BSD
from
litex.build.generic_platform
import
*
from
litex.build.lattice
import
LatticePlatform
from
litex.build.lattice.programmer
import
LatticeProgrammer
# IOs ----------------------------------------------------------------------------------------------
_io
=
[
(
"clk100"
,
0
,
Pins
(
"B29"
),
IOStandard
(
"LVDS"
)),
# [broken on rev1.0 (non diff pair)]
(
"clk12"
,
0
,
Pins
(
"B3"
),
IOStandard
(
"LVCMOS33"
)),
(
"clkref"
,
0
,
Pins
(
"E17"
),
IOStandard
(
"LVCMOS33"
)),
(
"user_btn"
,
0
,
Pins
(
"Y32"
),
IOStandard
(
"SSTL135_I"
)),
(
"user_btn"
,
1
,
Pins
(
"W31"
),
IOStandard
(
"SSTL135_I"
)),
(
"user_btn"
,
2
,
Pins
(
"AD30"
),
IOStandard
(
"SSTL135_I"
)),
(
"user_btn"
,
3
,
Pins
(
"AD29"
),
IOStandard
(
"SSTL135_I"
)),
(
"user_dip"
,
0
,
Pins
(
"AE31"
),
IOStandard
(
"SSTL135_I"
)),
(
"user_dip"
,
1
,
Pins
(
"AE32"
),
IOStandard
(
"SSTL135_I"
)),
(
"user_dip"
,
2
,
Pins
(
"AD32"
),
IOStandard
(
"SSTL135_I"
)),
(
"user_dip"
,
3
,
Pins
(
"AC32"
),
IOStandard
(
"SSTL135_I"
)),
(
"user_dip"
,
4
,
Pins
(
"AB32"
),
IOStandard
(
"SSTL135_I"
)),
(
"user_dip"
,
5
,
Pins
(
"AB31"
),
IOStandard
(
"SSTL135_I"
)),
(
"user_dip"
,
6
,
Pins
(
"AC31"
),
IOStandard
(
"SSTL135_I"
)),
(
"user_dip"
,
7
,
Pins
(
"AC30"
),
IOStandard
(
"SSTL135_I"
)),
(
"user_led"
,
0
,
Pins
(
"C26"
),
IOStandard
(
"LVCMOS33"
),
Misc
(
"PULLMODE=NONE"
)),
(
"user_led"
,
1
,
Pins
(
"D26"
),
IOStandard
(
"LVCMOS33"
),
Misc
(
"PULLMODE=NONE"
)),
(
"user_led"
,
2
,
Pins
(
"A28"
),
IOStandard
(
"LVCMOS33"
),
Misc
(
"PULLMODE=NONE"
)),
(
"user_led"
,
3
,
Pins
(
"A29"
),
IOStandard
(
"LVCMOS33"
),
Misc
(
"PULLMODE=NONE"
)),
(
"user_led"
,
4
,
Pins
(
"A30"
),
IOStandard
(
"LVCMOS33"
),
Misc
(
"PULLMODE=NONE"
)),
(
"user_led"
,
5
,
Pins
(
"AK29"
),
IOStandard
(
"LVCMOS33"
),
Misc
(
"PULLMODE=NONE"
)),
(
"user_led"
,
6
,
Pins
(
"AH32"
),
IOStandard
(
"LVCMOS33"
),
Misc
(
"PULLMODE=NONE"
)),
(
"user_led"
,
7
,
Pins
(
"AH30"
),
IOStandard
(
"LVCMOS33"
),
Misc
(
"PULLMODE=NONE"
)),
(
"user_led"
,
8
,
Pins
(
"AH28"
),
IOStandard
(
"LVCMOS33"
),
Misc
(
"PULLMODE=NONE"
)),
(
"user_led"
,
9
,
Pins
(
"AG30"
),
IOStandard
(
"LVCMOS33"
),
Misc
(
"PULLMODE=NONE"
)),
(
"user_led"
,
10
,
Pins
(
"AG29"
),
IOStandard
(
"LVCMOS33"
),
Misc
(
"PULLMODE=NONE"
)),
(
"user_led"
,
11
,
Pins
(
"AK30"
),
IOStandard
(
"LVCMOS33"
),
Misc
(
"PULLMODE=NONE"
)),
(
"serial"
,
0
,
Subsignal
(
"rx"
,
Pins
(
"AM28"
),
IOStandard
(
"LVCMOS33"
)),
Subsignal
(
"tx"
,
Pins
(
"AL28"
),
IOStandard
(
"LVCMOS33"
)),
),
(
"ftdi"
,
0
,
Subsignal
(
"dq"
,
Pins
(
"AM28 AL28 AM29 AK28 AK32 AM30 AJ32 AL30"
),
IOStandard
(
"LVCMOS33"
)),
Subsignal
(
"txe_n"
,
Pins
(
"AM31"
),
IOStandard
(
"LVCMOS33"
)),
Subsignal
(
"rxf_n"
,
Pins
(
"AJ31"
),
IOStandard
(
"LVCMOS33"
)),
Subsignal
(
"rd_n"
,
Pins
(
"AL32"
),
IOStandard
(
"LVCMOS33"
)),
Subsignal
(
"wr_n"
,
Pins
(
"AG28"
),
IOStandard
(
"LVCMOS33"
)),
Subsignal
(
"siwu_n"
,
Pins
(
"AJ28"
),
IOStandard
(
"LVCMOS33"
)),
),
(
"ddram"
,
0
,
Subsignal
(
"a"
,
Pins
(
"E30 F28 C32 E29 F32 D30 E32 D29"
,
"D32 C31 H32 F31 F29 B32 D31"
),
IOStandard
(
"SSTL135_I"
)),
Subsignal
(
"ba"
,
Pins
(
"H31 H30 J30"
),
IOStandard
(
"SSTL135_I"
)),
Subsignal
(
"ras_n"
,
Pins
(
"K31"
),
IOStandard
(
"SSTL135_I"
)),
Subsignal
(
"cas_n"
,
Pins
(
"K30"
),
IOStandard
(
"SSTL135_I"
)),
Subsignal
(
"we_n"
,
Pins
(
"J32"
),
IOStandard
(
"SSTL135_I"
)),
Subsignal
(
"cs_n"
,
Pins
(
"K29"
),
IOStandard
(
"SSTL135_I"
)),
Subsignal
(
"dm"
,
Pins
(
"R26 L27 Y27 U31"
),
IOStandard
(
"SSTL135_I"
)),
Subsignal
(
"dq"
,
Pins
(
" V26 R27 V27 T26 U28 T27 T29 U26"
,
" P27 K28 P26 L26 K27 N26 L29 K26"
,
"AC27 W28 AC26 Y26 AB26 W29 AD26 Y28"
,
" T32 U32 P31 V32 P32 W32 N32 U30"
),
IOStandard
(
"SSTL135_I"
),
Misc
(
"TERMINATION=75"
)),
Subsignal
(
"dqs_p"
,
Pins
(
"R29 N30 AB28 R32"
),
IOStandard
(
"SSTL135D_I"
),
Misc
(
"TERMINATION=OFF"
),
Misc
(
"DIFFRESISTOR=100"
)),
Subsignal
(
"clk_p"
,
Pins
(
"L31"
),
IOStandard
(
"SSTL135D_I"
)),
Subsignal
(
"cke"
,
Pins
(
"K32"
),
IOStandard
(
"SSTL135_I"
)),
Subsignal
(
"odt"
,
Pins
(
"J29"
),
IOStandard
(
"SSTL135_I"
)),
Subsignal
(
"reset_n"
,
Pins
(
"L32"
),
IOStandard
(
"SSTL135_I"
)),
Misc
(
"SLEWRATE=FAST"
),
),
(
"dram_vtt_en"
,
0
,
Pins
(
"E25"
),
IOStandard
(
"LVCMOS33"
)),
(
"eth_clocks"
,
0
,
Subsignal
(
"tx"
,
Pins
(
"A15"
)),
Subsignal
(
"rx"
,
Pins
(
"C17"
)),
Subsignal
(
"ref"
,
Pins
(
"A17"
)),
IOStandard
(
"LVCMOS33"
)
),
(
"eth"
,
0
,
Subsignal
(
"rst_n"
,
Pins
(
"D16"
)),
Subsignal
(
"int_n"
,
Pins
(
"E16"
)),
Subsignal
(
"mdio"
,
Pins
(
"F17"
)),
Subsignal
(
"mdc"
,
Pins
(
"B17"
)),
Subsignal
(
"rx_ctl"
,
Pins
(
"A16"
)),
Subsignal
(
"rx_data"
,
Pins
(
"C16 B16 B14 F16"
)),
Subsignal
(
"tx_ctl"
,
Pins
(
"D15"
)),
Subsignal
(
"tx_data"
,
Pins
(
"A14 F15 C15 C14"
)),
IOStandard
(
"LVCMOS33"
)
),
(
"clkgen"
,
0
,
Subsignal
(
"sda"
,
Pins
(
"C22"
)),
Subsignal
(
"scl"
,
Pins
(
"A22"
)),
Subsignal
(
"sd_oe"
,
Pins
(
"A2"
)),
IOStandard
(
"LVCMOS33"
)
),
(
"pcie_x2"
,
0
,
Subsignal
(
"clk_p"
,
Pins
(
"AM14"
)),
Subsignal
(
"clk_n"
,
Pins
(
"AM15"
)),
Subsignal
(
"rx_p"
,
Pins
(
"AM8 AK12"
)),
Subsignal
(
"rx_n"
,
Pins
(
"AM9 AK13"
)),
Subsignal
(
"tx_p"
,
Pins
(
"AK9 AM11"
)),
Subsignal
(
"tx_n"
,
Pins
(
"AK10 AM12"
)),
Subsignal
(
"perst"
,
Pins
(
"D22"
),
IOStandard
(
"LVCMOS33"
)),
Subsignal
(
"wake_n"
,
Pins
(
"A23"
),
IOStandard
(
"LVCMOS33"
)),
),
(
"m2"
,
0
,
Subsignal
(
"clk_p"
,
Pins
(
"AM23"
)),
Subsignal
(
"clk_n"
,
Pins
(
"AM24"
)),
Subsignal
(
"rx_p"
,
Pins
(
"AM17 AK21"
)),
Subsignal
(
"rx_n"
,
Pins
(
"AM18 AK22"
)),
Subsignal
(
"tx_p"
,
Pins
(
"AK18 AM20"
)),
Subsignal
(
"tx_n"
,
Pins
(
"AK19 AM21"
)),
Subsignal
(
"clksel"
,
Pins
(
"N3"
),
IOStandard
(
"LVCMOS33"
)),
Subsignal
(
"sdio_clk"
,
Pins
(
"L4"
),
IOStandard
(
"LVCMOS33"
)),
Subsignal
(
"sdio_cmd"
,
Pins
(
"K4"
),
IOStandard
(
"LVCMOS33"
)),
Subsignal
(
"sdio_dq"
,
Pins
(
"L7 N4 L6 N6"
),
IOStandard
(
"LVCMOS33"
)),
Subsignal
(
"uart_tx"
,
Pins
(
"P6"
),
IOStandard
(
"LVCMOS33"
)),
Subsignal
(
"uart_rx"
,
Pins
(
"K5"
),
IOStandard
(
"LVCMOS33"
)),
Subsignal
(
"uart_rts_n"
,
Pins
(
"N7"
),
IOStandard
(
"LVCMOS33"
)),
Subsignal
(
"uart_cts_n"
,
Pins
(
"P7"
),
IOStandard
(
"LVCMOS33"
))
),
(
"sdcard"
,
0
,
Subsignal
(
"data"
,
Pins
(
"AG1 AJ1 AH1 AK1"
)),
Subsignal
(
"clk"
,
Pins
(
"AK3"
)),
Subsignal
(
"cmd"
,
Pins
(
"AH3"
)),
IOStandard
(
"LVCMOS33"
)
),
(
"spiflash4x"
,
0
,
Subsignal
(
"clk"
,
Pins
(
"AM3"
)),
Subsignal
(
"cs_n"
,
Pins
(
"AJ3"
)),
Subsignal
(
"dq"
,
Pins
(
"AK2 AJ2 AM2 AL1"
)),
IOStandard
(
"LVCMOS33"
)
),
(
"spiflash"
,
0
,
Subsignal
(
"clk"
,
Pins
(
"AM3"
)),
Subsignal
(
"cs_n"
,
Pins
(
"AJ3"
)),
Subsignal
(
"mosi"
,
Pins
(
"AK2"
)),
Subsignal
(
"miso"
,
Pins
(
"AJ2"
)),
Subsignal
(
"wp"
,
Pins
(
"AM2"
)),
Subsignal
(
"hold"
,
Pins
(
"AL1"
)),
IOStandard
(
"LVCMOS33"
)
),
(
"ulpi"
,
0
,
Subsignal
(
"clk"
,
Pins
(
"A18"
)),
Subsignal
(
"stp"
,
Pins
(
"D18"
)),
Subsignal
(
"dir"
,
Pins
(
"C18"
)),
Subsignal
(
"nxt"
,
Pins
(
"F18"
)),
Subsignal
(
"reset"
,
Pins
(
"D17"
)),
Subsignal
(
"data"
,
Pins
(
"C20 C19 E19 D20 A20 B19 D19 A19"
)),
IOStandard
(
"LVCMOS33"
)
),
(
"hdmi"
,
0
,
Subsignal
(
"d"
,
Pins
(
"C11 A11 B11 A10 B10 C10 A8 B7"
,
"B8 A7 C8 C9 F11 E11 E10 D10"
,
"F10 F9 D9 D8 C7 F8 E8 D11"
)),
Subsignal
(
"de"
,
Pins
(
"F14"
)),
Subsignal
(
"clk"
,
Pins
(
"A9"
)),
Subsignal
(
"vsync"
,
Pins
(
"E14"
)),
Subsignal
(
"hsync"
,
Pins
(
"F13"
)),
Subsignal
(
"sda"
,
Pins
(
"D13"
)),
Subsignal
(
"scl"
,
Pins
(
"C13"
)),
IOStandard
(
"LVCMOS33"
)
),
]
_connectors
=
[
(
"pmoda"
,
"F19 F20 B22 C23 D14 A13 E22 D23"
),
(
"pmodb"
,
"C25 A26 F23 F25 B25 D25 F22 F24"
),
(
"pmodx"
,
"A24 C24 D24 B23 D23 A25"
),
(
"ext0"
,
"T1 U1 AE5 AE4 AB5 AB6 Y5 W5 W2 Y1 AB7 AC6 AB3 AB4 AD3 AE3 AB1 AC1 AD1 AE1 AD6 AE6 AC7 AD7"
),
(
"ext1"
,
"P5 P4 R7 T7 R6 T6 U6 U7 R4 T5 T4 U5 U4 V4 V6 V7 P2 P3 R3 T3 N1 P1 U2 U3"
),
(
"ext2"
,
"K6 K7 J7 J6 H6 H5 F4 F5 F3 E3 C4 C3 C5 D5 D3 D2 H2 H3 J3 K3 B1 C2 F1 H1"
)
]
# Platform -----------------------------------------------------------------------------------------
class
Platform
(
LatticePlatform
):
default_clk_name
=
"clk12"
default_clk_period
=
83
def
__init__
(
self
,
**
kwargs
):
LatticePlatform
.
__init__
(
self
,
"LFE5UM5G-85F-8BG756C"
,
_io
,
_connectors
,
**
kwargs
)
def
do_finalize
(
self
,
fragment
):
try
:
self
.
add_period_constraint
(
self
.
lookup_request
(
"eth_clocks"
,
0
).
rx
,
1e9
/
125e6
)
except
ConstraintError
:
pass
This diff is collapsed.
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litex_boards/community/targets/ac701.py
View file @
82d73b83
#!/usr/bin/env python3
# This file is Copyright (c) 2019 Vamsi K Vytla <vamsi.vytla@gmail.com>
# This file is Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
# License: BSD
import
argparse
from
migen
import
*
...
...
@@ -17,7 +21,7 @@ from litedram.phy import s7ddrphy
from
liteeth.phy.a7_gtp
import
QPLLSettings
,
QPLL
from
liteeth.phy.a7_1000basex
import
A7_1000BASEX
from
liteeth.phy.s7rgmii
import
LiteEthPHYRGMII
from
liteeth.
core.
mac
import
LiteEthMAC
from
liteeth.mac
import
LiteEthMAC
# CRG ----------------------------------------------------------------------------------------------
...
...
This diff is collapsed.
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litex_boards/community/targets/de10lite.py
View file @
82d73b83
#!/usr/bin/env python3
# This file is Copyright (c) 2019 msloniewski <marcin.sloniewski@gmail.com>
# License: BSD
import
argparse
from
migen
import
*
...
...
This diff is collapsed.
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litex_boards/community/targets/de1soc.py
View file @
82d73b83
#!/usr/bin/env python3
#
# SPDX-License-Identifier: BSD-2-Clause
#
# Copyright (C) 2019 Antony Pavlov <antonynpavlov@gmail.com>
#
# based on litex/boards/platforms/de0nano.py
#
# This file is Copyright (c) 2019 Antony Pavlov <antonynpavlov@gmail.com>
# License: BSD
import
argparse
...
...
This diff is collapsed.
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litex_boards/community/targets/de2_115.py
View file @
82d73b83
#!/usr/bin/env python3
#
# SPDX-License-Identifier: BSD-2-Clause
#
# Copyright (C) 2019 Antony Pavlov <antonynpavlov@gmail.com>
#
# based on litex/boards/platforms/de0nano.py
#
# This file is Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr>
# License: BSD
import
argparse
...
...
This diff is collapsed.
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litex_boards/community/targets/trellisboard.py
0 → 100644
View file @
82d73b83
#!/usr/bin/env python3
import
argparse
from
migen
import
*
from
migen.genlib.resetsync
import
AsyncResetSynchronizer
from
litex_boards.community.platforms
import
trellisboard
from
litex.soc.cores.clock
import
*
from
litex.soc.integration.soc_core
import
mem_decoder
from
litex.soc.integration.soc_sdram
import
*
from
litex.soc.integration.builder
import
*
from
litedram.modules
import
MT41J256M16
from
litedram.phy
import
ECP5DDRPHY
from
liteeth.phy.ecp5rgmii
import
LiteEthPHYRGMII
from
liteeth.core.mac
import
LiteEthMAC
# CRG ----------------------------------------------------------------------------------------------
class
_CRG
(
Module
):
def
__init__
(
self
,
platform
,
sys_clk_freq
):
self
.
clock_domains
.
cd_init
=
ClockDomain
()
self
.
clock_domains
.
cd_por
=
ClockDomain
(
reset_less
=
True
)
self
.
clock_domains
.
cd_sys
=
ClockDomain
()
self
.
clock_domains
.
cd_sys2x
=
ClockDomain
()
self
.
clock_domains
.
cd_sys2x_i
=
ClockDomain
(
reset_less
=
True
)
# # #
self
.
cd_init
.
clk
.
attr
.
add
(
"keep"
)
self
.
cd_por
.
clk
.
attr
.
add
(
"keep"
)
self
.
cd_sys
.
clk
.
attr
.
add
(
"keep"
)
self
.
cd_sys2x
.
clk
.
attr
.
add
(
"keep"
)
self
.
cd_sys2x_i
.
clk
.
attr
.
add
(
"keep"
)
self
.
stop
=
Signal
()
# clk / rst
clk12
=
platform
.
request
(
"clk12"
)
rst
=
platform
.
request
(
"user_btn"
,
0
)
platform
.
add_period_constraint
(
clk12
,
1e9
/
12e6
)
# power on reset
por_count
=
Signal
(
16
,
reset
=
2
**
16
-
1
)
por_done
=
Signal
()
self
.
comb
+=
self
.
cd_por
.
clk
.
eq
(
ClockSignal
())
self
.
comb
+=
por_done
.
eq
(
por_count
==
0
)
self
.
sync
.
por
+=
If
(
~
por_done
,
por_count
.
eq
(
por_count
-
1
))
# pll
self
.
submodules
.
pll
=
pll
=
ECP5PLL
()
pll
.
register_clkin
(
clk12
,
12e6
)
pll
.
create_clkout
(
self
.
cd_sys2x_i
,
2
*
sys_clk_freq
)
pll
.
create_clkout
(
self
.
cd_init
,
25e6
)
self
.
specials
+=
[
Instance
(
"ECLKSYNCB"
,
i_ECLKI
=
self
.
cd_sys2x_i
.
clk
,
i_STOP
=
self
.
stop
,
o_ECLKO
=
self
.
cd_sys2x
.
clk
),
Instance
(
"CLKDIVF"
,
p_DIV
=
"2.0"
,
i_ALIGNWD
=
0
,
i_CLKI
=
self
.
cd_sys2x
.
clk
,
i_RST
=
self
.
cd_sys2x
.
rst
,
o_CDIVX
=
self
.
cd_sys
.
clk
),
AsyncResetSynchronizer
(
self
.
cd_init
,
~
por_done
|
~
pll
.
locked
|
rst
),
AsyncResetSynchronizer
(
self
.
cd_sys
,
~
por_done
|
~
pll
.
locked
|
rst
)
]
vtt_en
=
platform
.
request
(
"dram_vtt_en"
)
self
.
comb
+=
vtt_en
.
eq
(
1
)
# BaseSoC ------------------------------------------------------------------------------------------
class
BaseSoC
(
SoCSDRAM
):
def
__init__
(
self
,
sys_clk_freq
=
int
(
75e6
),
toolchain
=
"diamond"
,
**
kwargs
):
platform
=
trellisboard
.
Platform
(
toolchain
=
toolchain
)
SoCSDRAM
.
__init__
(
self
,
platform
,
clk_freq
=
sys_clk_freq
,
integrated_rom_size
=
0x8000
,
**
kwargs
)
# crg
crg
=
_CRG
(
platform
,
sys_clk_freq
)
self
.
submodules
.
crg
=
crg
# sdram
self
.
submodules
.
ddrphy
=
ECP5DDRPHY
(
platform
.
request
(
"ddram"
),
sys_clk_freq
=
sys_clk_freq
)
self
.
add_csr
(
"ddrphy"
)
self
.
add_constant
(
"ECP5DDRPHY"
,
None
)
self
.
comb
+=
crg
.
stop
.
eq
(
self
.
ddrphy
.
init
.
stop
)
sdram_module
=
MT41J256M16
(
sys_clk_freq
,
"1:2"
)
self
.
register_sdram
(
self
.
ddrphy
,
sdram_module
.
geom_settings
,
sdram_module
.
timing_settings
)
class
EthernetSoC
(
BaseSoC
):
mem_map
=
{
"ethmac"
:
0x30000000
,
# (shadow @0xb0000000)
}
mem_map
.
update
(
BaseSoC
.
mem_map
)
def
__init__
(
self
,
toolchain
=
"diamond"
,
**
kwargs
):
BaseSoC
.
__init__
(
self
,
toolchain
=
toolchain
,
**
kwargs
)
self
.
submodules
.
ethphy
=
LiteEthPHYRGMII
(
self
.
platform
.
request
(
"eth_clocks"
),
self
.
platform
.
request
(
"eth"
))
self
.
add_csr
(
"ethphy"
)
self
.
submodules
.
ethmac
=
LiteEthMAC
(
phy
=
self
.
ethphy
,
dw
=
32
,
interface
=
"wishbone"
,
endianness
=
self
.
cpu
.
endianness
)
self
.
add_wb_slave
(
self
.
mem_map
[
"ethmac"
],
self
.
ethmac
.
bus
,
0x2000
)
self
.
add_memory_region
(
"ethmac"
,
self
.
mem_map
[
"ethmac"
]
|
self
.
shadow_base
,
0x2000
)
self
.
add_csr
(
"ethmac"
)
self
.
add_interrupt
(
"ethmac"
)
self
.
ethphy
.
crg
.
cd_eth_rx
.
clk
.
attr
.
add
(
"keep"
)
self
.
ethphy
.
crg
.
cd_eth_tx
.
clk
.
attr
.
add
(
"keep"
)
self
.
platform
.
add_period_constraint
(
self
.
ethphy
.
crg
.
cd_eth_rx
.
clk
,
1e9
/
125e6
)
self
.
platform
.
add_period_constraint
(
self
.
ethphy
.
crg
.
cd_eth_tx
.
clk
,
1e9
/
125e6
)
# Build --------------------------------------------------------------------------------------------
def
main
():
parser
=
argparse
.
ArgumentParser
(
description
=
"LiteX SoC on Versa ECP5"
)
parser
.
add_argument
(
"--gateware-toolchain"
,
dest
=
"toolchain"
,
default
=
"diamond"
,
help
=
'gateware toolchain to use, diamond (default) or trellis'
)
builder_args
(
parser
)
soc_sdram_args
(
parser
)
parser
.
add_argument
(
"--sys-clk-freq"
,
default
=
75e6
,
help
=
"system clock frequency (default=75MHz)"
)
parser
.
add_argument
(
"--with-ethernet"
,
action
=
"store_true"
,
help
=
"enable Ethernet support"
)
args
=
parser
.
parse_args
()
cls
=
EthernetSoC
if
args
.
with_ethernet
else
BaseSoC
soc
=
cls
(
toolchain
=
args
.
toolchain
,
sys_clk_freq
=
int
(
float
(
args
.
sys_clk_freq
)),
**
soc_sdram_argdict
(
args
))
builder
=
Builder
(
soc
,
**
builder_argdict
(
args
))
builder
.
build
()
if
__name__
==
"__main__"
:
main
()
This diff is collapsed.
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litex_boards/official/targets/simple.py
0 → 100755
View file @
82d73b83
#!/usr/bin/env python3
# This file is Copyright (c) 2014-2019 Florent Kermarrec <florent@enjoy-digital.fr>
# This file is Copyright (c) 2013-2014 Sebastien Bourdeauducq <sb@m-labs.hk>
# License: BSD
import
argparse
import
importlib
from
migen
import
*
from
migen.genlib.io
import
CRG
from
litex.soc.integration.soc_core
import
*
from
litex.soc.integration.builder
import
*
from
liteeth.phy
import
LiteEthPHY
from
liteeth.mac
import
LiteEthMAC
# BaseSoC ------------------------------------------------------------------------------------------
class
BaseSoC
(
SoCCore
):
def
__init__
(
self
,
platform
,
**
kwargs
):
sys_clk_freq
=
int
(
1e9
/
platform
.
default_clk_period
)
SoCCore
.
__init__
(
self
,
platform
,
clk_freq
=
sys_clk_freq
,
integrated_rom_size
=
0x8000
,
integrated_main_ram_size
=
16
*
1024
,
**
kwargs
)
self
.
submodules
.
crg
=
CRG
(
platform
.
request
(
platform
.
default_clk_name
))
# EthernetSoC --------------------------------------------------------------------------------------
class
EthernetSoC
(
BaseSoC
):
mem_map
=
{
"ethmac"
:
0x30000000
,
# (shadow @0xb0000000)
}
mem_map
.
update
(
BaseSoC
.
mem_map
)
def
__init__
(
self
,
platform
,
**
kwargs
):
BaseSoC
.
__init__
(
self
,
platform
,
**
kwargs
)
self
.
submodules
.
ethphy
=
LiteEthPHY
(
platform
.
request
(
"eth_clocks"
),
platform
.
request
(
"eth"
))
self
.
add_csr
(
"ethphy"
)
self
.
submodules
.
ethmac
=
LiteEthMAC
(
phy
=
self
.
ethphy
,
dw
=
32
,
interface
=
"wishbone"
,
endianness
=
self
.
cpu
.
endianness
,
with_preamble_crc
=
False
)
self
.
add_wb_slave
(
mem_decoder
(
self
.
mem_map
[
"ethmac"
]),
self
.
ethmac
.
bus
)
self
.
add_memory_region
(
"ethmac"
,
self
.
mem_map
[
"ethmac"
]
|
self
.
shadow_base
,
0x2000
)
self
.
add_csr
(
"ethmac"
)
self
.
add_interrupt
(
"ethmac"
)
# Build --------------------------------------------------------------------------------------------
def
main
():
parser
=
argparse
.
ArgumentParser
(
description
=
"Generic LiteX SoC"
)
builder_args
(
parser
)
soc_core_args
(
parser
)
parser
.
add_argument
(
"--with-ethernet"
,
action
=
"store_true"
,
help
=
"enable Ethernet support"
)
parser
.
add_argument
(
"platform"
,
help
=
"module name of the platform to build for"
)
parser
.
add_argument
(
"--gateware-toolchain"
,
default
=
None
,
help
=
"FPGA gateware toolchain used for build"
)
args
=
parser
.
parse_args
()
platform_module
=
importlib
.
import_module
(
args
.
platform
)
if
args
.
gateware_toolchain
is
not
None
:
platform
=
platform_module
.
Platform
(
toolchain
=
args
.
gateware_toolchain
)
else
:
platform
=
platform_module
.
Platform
()
cls
=
EthernetSoC
if
args
.
with_ethernet
else
BaseSoC
soc
=
cls
(
platform
,
**
soc_core_argdict
(
args
))
builder
=
Builder
(
soc
,
**
builder_argdict
(
args
))
builder
.
build
()
if
__name__
==
"__main__"
:
main
()
This diff is collapsed.
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litex_boards/partner/__init__.py
0 → 100644
View file @
82d73b83
This diff is collapsed.
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litex_boards/partner/platforms/__init__.py
0 → 100644
View file @
82d73b83
This diff is collapsed.
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litex_boards/partner/platforms/fomu_evt.py
View file @
82d73b83
# This file is Copyright (c) 2019 Tom Keddie <git@bronwenandtom.com>
# This file is Copyright (c) 2019 Sean Cross <sean@xobs.io>
# License: BSD
# fomu evt board from from crowd funding
# design files at https://github.com/im-tomu/fomu-hardware/tree/evt/hardware/pcb
#
...
...
@@ -7,7 +11,7 @@ from litex.build.lattice.programmer import IceStormProgrammer
_io
=
[
(
"rgb_led
_n
"
,
0
,
(
"rgb_led"
,
0
,
Subsignal
(
"r"
,
Pins
(
"40"
)),
Subsignal
(
"g"
,
Pins
(
"39"
)),
Subsignal
(
"b"
,
Pins
(
"41"
)),
...
...
This diff is collapsed.
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litex_boards/partner/platforms/fomu_hacker.py
View file @
82d73b83
# This file is Copyright (c) 2019 Tom Keddie <git@bronwenandtom.com>
# License: BSD
# fomu hacker board
# schematic at https://github.com/im-tomu/fomu-hardware/tree/master/hacker/releases/v0.0-19-g154fecc
#
...
...
This diff is collapsed.
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litex_boards/partner/platforms/fomu_pvt.py
View file @
82d73b83
# This file is Copyright (c) 2019 Tom Keddie <git@bronwenandtom.com>
# License: BSD
# fomu pvt board from crowd funding
# design files at https://github.com/im-tomu/fomu-hardware/tree/pvt/hardware/pcb
#
...
...
This diff is collapsed.
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litex_boards/partner/targets/__init__.py
0 → 100644
View file @
82d73b83
This diff is collapsed.
Click to expand it.
litex_boards/partner/targets/fomu.py
0 → 100644
View file @
82d73b83
# This file is Copyright (c) 2019 Sean Cross <sean@xobs.io>
# License: BSD
from
litex_boards.partner.platforms
import
netv2
from
migen
import
Module
,
Signal
,
Instance
,
ClockDomain
,
If
from
migen.genlib.resetsync
import
AsyncResetSynchronizer
# CRG ----------------------------------------------------------------------------------------------
class
_CRG
(
Module
):
def
__init__
(
self
,
platform
,
use_pll
=
True
):
clk48_raw
=
platform
.
request
(
"clk48"
)
clk12_raw
=
Signal
()
clk48
=
Signal
()
clk12
=
Signal
()
reset_delay
=
Signal
(
13
,
reset
=
4095
)
self
.
clock_domains
.
cd_por
=
ClockDomain
()
self
.
reset
=
Signal
()
self
.
clock_domains
.
cd_sys
=
ClockDomain
()
self
.
clock_domains
.
cd_usb_12
=
ClockDomain
()
self
.
clock_domains
.
cd_usb_48
=
ClockDomain
()
platform
.
add_period_constraint
(
self
.
cd_usb_48
.
clk
,
1e9
/
48e6
)
platform
.
add_period_constraint
(
self
.
cd_sys
.
clk
,
1e9
/
12e6
)
platform
.
add_period_constraint
(
self
.
cd_usb_12
.
clk
,
1e9
/
12e6
)
platform
.
add_period_constraint
(
clk48
,
1e9
/
48e6
)
platform
.
add_period_constraint
(
clk48_raw
,
1e9
/
48e6
)
platform
.
add_period_constraint
(
clk12_raw
,
1e9
/
12e6
)
# POR reset logic- POR generated from sys clk, POR logic feeds sys clk
# reset.
self
.
comb
+=
[
self
.
cd_por
.
clk
.
eq
(
self
.
cd_sys
.
clk
),
self
.
cd_sys
.
rst
.
eq
(
reset_delay
!=
0
),
self
.
cd_usb_12
.
rst
.
eq
(
reset_delay
!=
0
),
]
if
use_pll
:
# Divide clk48 down to clk12, to ensure they're synchronized.
# By doing this, we avoid needing clock-domain crossing.
clk12_counter
=
Signal
(
2
)
self
.
clock_domains
.
cd_usb_48_raw
=
ClockDomain
()
platform
.
add_period_constraint
(
self
.
cd_usb_48_raw
.
clk
,
1e9
/
48e6
)
# POR reset logic- POR generated from sys clk, POR logic feeds sys clk
# reset.
self
.
comb
+=
[
self
.
cd_usb_48
.
rst
.
eq
(
reset_delay
!=
0
),
]
self
.
comb
+=
self
.
cd_usb_48_raw
.
clk
.
eq
(
clk48_raw
)
self
.
comb
+=
self
.
cd_usb_48
.
clk
.
eq
(
clk48
)
self
.
sync
.
usb_48_raw
+=
clk12_counter
.
eq
(
clk12_counter
+
1
)
self
.
comb
+=
clk12_raw
.
eq
(
clk12_counter
[
1
])
self
.
specials
+=
Instance
(
"SB_GB"
,
i_USER_SIGNAL_TO_GLOBAL_BUFFER
=
clk12_raw
,
o_GLOBAL_BUFFER_OUTPUT
=
clk12
,
)
self
.
specials
+=
Instance
(
"SB_PLL40_CORE"
,
# Parameters
p_DIVR
=
0
,
p_DIVF
=
3
,
p_DIVQ
=
2
,
p_FILTER_RANGE
=
1
,
p_FEEDBACK_PATH
=
"PHASE_AND_DELAY"
,
p_DELAY_ADJUSTMENT_MODE_FEEDBACK
=
"FIXED"
,
p_FDA_FEEDBACK
=
15
,
p_DELAY_ADJUSTMENT_MODE_RELATIVE
=
"FIXED"
,
p_FDA_RELATIVE
=
0
,
p_SHIFTREG_DIV_MODE
=
1
,
p_PLLOUT_SELECT
=
"SHIFTREG_0deg"
,
p_ENABLE_ICEGATE
=
0
,
# IO
i_REFERENCECLK
=
clk12
,
o_PLLOUTGLOBAL
=
clk48
,
i_BYPASS
=
0
,
i_RESETB
=
1
,
)
else
:
self
.
specials
+=
Instance
(
"SB_GB"
,
i_USER_SIGNAL_TO_GLOBAL_BUFFER
=
clk48_raw
,
o_GLOBAL_BUFFER_OUTPUT
=
clk48
,
)
self
.
comb
+=
self
.
cd_usb_48
.
clk
.
eq
(
clk48
)
clk12_counter
=
Signal
(
2
)
self
.
sync
.
usb_48
+=
clk12_counter
.
eq
(
clk12_counter
+
1
)
self
.
comb
+=
clk12_raw
.
eq
(
clk12_counter
[
1
])
self
.
specials
+=
Instance
(
"SB_GB"
,
i_USER_SIGNAL_TO_GLOBAL_BUFFER
=
clk12_raw
,
o_GLOBAL_BUFFER_OUTPUT
=
clk12
,
)
self
.
comb
+=
self
.
cd_sys
.
clk
.
eq
(
clk12
)
self
.
comb
+=
self
.
cd_usb_12
.
clk
.
eq
(
clk12
)
self
.
sync
.
por
+=
\
If
(
reset_delay
!=
0
,
reset_delay
.
eq
(
reset_delay
-
1
)
)
self
.
specials
+=
AsyncResetSynchronizer
(
self
.
cd_por
,
self
.
reset
)
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