Commit 30ea463b authored by Florent Kermarrec's avatar Florent Kermarrec
Browse files

targets: keep attributes are no longer needed since automatically added when...

targets: keep attributes are no longer needed since automatically added when applying constraints to signals.
parent 8fa3f092
...@@ -34,10 +34,6 @@ class _CRG(Module): ...@@ -34,10 +34,6 @@ class _CRG(Module):
# # # # # #
self.cd_sys.clk.attr.add("keep")
self.cd_sys4x.clk.attr.add("keep")
self.cd_sys4x_dqs.clk.attr.add("keep")
self.submodules.pll = pll = S7PLL(speedgrade=-1) self.submodules.pll = pll = S7PLL(speedgrade=-1)
self.comb += pll.reset.eq(~platform.request("cpu_reset")) self.comb += pll.reset.eq(~platform.request("cpu_reset"))
pll.register_clkin(platform.request("clk200"), 200e6) pll.register_clkin(platform.request("clk200"), 200e6)
...@@ -92,8 +88,6 @@ class EthernetSoC(BaseSoC): ...@@ -92,8 +88,6 @@ class EthernetSoC(BaseSoC):
self.submodules.ethphy = LiteEthPHYRGMII(self.platform.request("eth_clocks"), self.submodules.ethphy = LiteEthPHYRGMII(self.platform.request("eth_clocks"),
self.platform.request("eth")) self.platform.request("eth"))
self.add_csr("ethphy") self.add_csr("ethphy")
self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6)
self.platform.add_false_path_constraints( self.platform.add_false_path_constraints(
......
...@@ -25,10 +25,6 @@ class _CRG(Module): ...@@ -25,10 +25,6 @@ class _CRG(Module):
# # # # # #
self.cd_sys.clk.attr.add("keep")
self.cd_sys_ps.clk.attr.add("keep")
self.cd_por.clk.attr.add("keep")
# power on rst # power on rst
rst_n = Signal() rst_n = Signal()
self.sync.por += rst_n.eq(1) self.sync.por += rst_n.eq(1)
......
...@@ -25,10 +25,6 @@ class _CRG(Module): ...@@ -25,10 +25,6 @@ class _CRG(Module):
# # # # # #
self.cd_sys.clk.attr.add("keep")
self.cd_sys_ps.clk.attr.add("keep")
self.cd_por.clk.attr.add("keep")
# power on rst # power on rst
rst_n = Signal() rst_n = Signal()
self.sync.por += rst_n.eq(1) self.sync.por += rst_n.eq(1)
......
...@@ -25,10 +25,6 @@ class _CRG(Module): ...@@ -25,10 +25,6 @@ class _CRG(Module):
# # # # # #
self.cd_sys.clk.attr.add("keep")
self.cd_sys_ps.clk.attr.add("keep")
self.cd_por.clk.attr.add("keep")
# power on rst # power on rst
rst_n = Signal() rst_n = Signal()
self.sync.por += rst_n.eq(1) self.sync.por += rst_n.eq(1)
......
...@@ -22,8 +22,6 @@ class _CRG(Module): ...@@ -22,8 +22,6 @@ class _CRG(Module):
# # # # # #
self.cd_sys.clk.attr.add("keep")
# clk / rst # clk / rst
clk = clk12 = platform.request("clk12") clk = clk12 = platform.request("clk12")
rst_n = platform.request("rst_n") rst_n = platform.request("rst_n")
......
...@@ -32,10 +32,6 @@ class _CRG(Module): ...@@ -32,10 +32,6 @@ class _CRG(Module):
# # # # # #
self.cd_sys.clk.attr.add("keep")
self.cd_sys4x.clk.attr.add("keep")
self.cd_sys4x_dqs.clk.attr.add("keep")
self.submodules.pll = pll = S7PLL(speedgrade=-1) self.submodules.pll = pll = S7PLL(speedgrade=-1)
self.comb += pll.reset.eq(~platform.request("cpu_reset")) self.comb += pll.reset.eq(~platform.request("cpu_reset"))
pll.register_clkin(platform.request("clk100"), 100e6) pll.register_clkin(platform.request("clk100"), 100e6)
...@@ -97,8 +93,6 @@ class EthernetSoC(BaseSoC): ...@@ -97,8 +93,6 @@ class EthernetSoC(BaseSoC):
self.add_csr("ethmac") self.add_csr("ethmac")
self.add_interrupt("ethmac") self.add_interrupt("ethmac")
self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/12.5e6) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/12.5e6)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/12.5e6) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/12.5e6)
self.platform.add_false_path_constraints( self.platform.add_false_path_constraints(
......
...@@ -25,10 +25,6 @@ class _CRG(Module): ...@@ -25,10 +25,6 @@ class _CRG(Module):
# # # # # #
self.cd_sys.clk.attr.add("keep")
self.cd_sys_ps.clk.attr.add("keep")
self.cd_por.clk.attr.add("keep")
# Power on reset # Power on reset
rst_n = Signal() rst_n = Signal()
self.sync.por += rst_n.eq(1) self.sync.por += rst_n.eq(1)
......
...@@ -29,9 +29,6 @@ class _CRG(Module): ...@@ -29,9 +29,6 @@ class _CRG(Module):
# # # # # #
self.cd_sys.clk.attr.add("keep")
self.cd_sys4x.clk.attr.add("keep")
self.submodules.pll = pll = S7MMCM(speedgrade=-2) self.submodules.pll = pll = S7MMCM(speedgrade=-2)
self.comb += pll.reset.eq(~platform.request("cpu_reset_n")) self.comb += pll.reset.eq(~platform.request("cpu_reset_n"))
pll.register_clkin(platform.request("clk200"), 200e6) pll.register_clkin(platform.request("clk200"), 200e6)
...@@ -87,8 +84,6 @@ class EthernetSoC(BaseSoC): ...@@ -87,8 +84,6 @@ class EthernetSoC(BaseSoC):
self.add_csr("ethmac") self.add_csr("ethmac")
self.add_interrupt("ethmac") self.add_interrupt("ethmac")
self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6)
self.platform.add_false_path_constraints( self.platform.add_false_path_constraints(
......
...@@ -31,9 +31,6 @@ class _CRG(Module): ...@@ -31,9 +31,6 @@ class _CRG(Module):
# # # # # #
self.cd_sys.clk.attr.add("keep")
self.cd_sys4x.clk.attr.add("keep")
self.submodules.pll = pll = S7MMCM(speedgrade=-2) self.submodules.pll = pll = S7MMCM(speedgrade=-2)
self.comb += pll.reset.eq(platform.request("cpu_reset")) self.comb += pll.reset.eq(platform.request("cpu_reset"))
pll.register_clkin(platform.request("clk200"), 200e6) pll.register_clkin(platform.request("clk200"), 200e6)
...@@ -91,8 +88,6 @@ class EthernetSoC(BaseSoC): ...@@ -91,8 +88,6 @@ class EthernetSoC(BaseSoC):
self.add_csr("ethmac") self.add_csr("ethmac")
self.add_interrupt("ethmac") self.add_interrupt("ethmac")
self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6)
self.platform.add_false_path_constraints( self.platform.add_false_path_constraints(
......
...@@ -30,9 +30,6 @@ class _CRG(Module): ...@@ -30,9 +30,6 @@ class _CRG(Module):
# # # # # #
self.cd_sys.clk.attr.add("keep")
self.cd_sys4x.clk.attr.add("keep")
self.submodules.pll = pll = USMMCM(speedgrade=-2) self.submodules.pll = pll = USMMCM(speedgrade=-2)
self.comb += pll.reset.eq(platform.request("cpu_reset")) self.comb += pll.reset.eq(platform.request("cpu_reset"))
self.clock_domains.cd_pll4x = ClockDomain(reset_less=True) self.clock_domains.cd_pll4x = ClockDomain(reset_less=True)
...@@ -127,8 +124,6 @@ class EthernetSoC(BaseSoC): ...@@ -127,8 +124,6 @@ class EthernetSoC(BaseSoC):
self.add_csr("ethmac") self.add_csr("ethmac")
self.add_interrupt("ethmac") self.add_interrupt("ethmac")
self.ethphy.cd_eth_rx.clk.attr.add("keep")
self.ethphy.cd_eth_tx.clk.attr.add("keep")
self.platform.add_period_constraint(self.ethphy.cd_eth_rx.clk, 1e9/125e6) self.platform.add_period_constraint(self.ethphy.cd_eth_rx.clk, 1e9/125e6)
self.platform.add_period_constraint(self.ethphy.cd_eth_tx.clk, 1e9/125e6) self.platform.add_period_constraint(self.ethphy.cd_eth_tx.clk, 1e9/125e6)
self.platform.add_false_path_constraints( self.platform.add_false_path_constraints(
......
...@@ -29,9 +29,6 @@ class _CRG(Module): ...@@ -29,9 +29,6 @@ class _CRG(Module):
# # # # # #
self.cd_sys.clk.attr.add("keep")
self.cd_sys_ps.clk.attr.add("keep")
self.submodules.pll = pll = S6PLL(speedgrade=-1) self.submodules.pll = pll = S6PLL(speedgrade=-1)
pll.register_clkin(platform.request("clk32"), 32e6) pll.register_clkin(platform.request("clk32"), 32e6)
pll.create_clkout(self.cd_sys, clk_freq) pll.create_clkout(self.cd_sys, clk_freq)
......
...@@ -31,10 +31,6 @@ class _CRG(Module): ...@@ -31,10 +31,6 @@ class _CRG(Module):
# # # # # #
self.cd_sys.clk.attr.add("keep")
self.cd_sys2x.clk.attr.add("keep")
self.cd_sys2x_dqs.clk.attr.add("keep")
self.submodules.pll = pll = S7MMCM(speedgrade=-1) self.submodules.pll = pll = S7MMCM(speedgrade=-1)
self.comb += pll.reset.eq(~platform.request("cpu_reset")) self.comb += pll.reset.eq(~platform.request("cpu_reset"))
pll.register_clkin(platform.request("clk100"), 100e6) pll.register_clkin(platform.request("clk100"), 100e6)
...@@ -95,8 +91,6 @@ class EthernetSoC(BaseSoC): ...@@ -95,8 +91,6 @@ class EthernetSoC(BaseSoC):
self.add_csr("ethmac") self.add_csr("ethmac")
self.add_interrupt("ethmac") self.add_interrupt("ethmac")
self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/12.5e6) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/12.5e6)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/12.5e6) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/12.5e6)
self.platform.add_false_path_constraints( self.platform.add_false_path_constraints(
......
...@@ -31,10 +31,6 @@ class _CRG(Module): ...@@ -31,10 +31,6 @@ class _CRG(Module):
# # # # # #
self.cd_sys.clk.attr.add("keep")
self.cd_sys4x.clk.attr.add("keep")
self.cd_sys4x_dqs.clk.attr.add("keep")
self.submodules.pll = pll = S7MMCM(speedgrade=-1) self.submodules.pll = pll = S7MMCM(speedgrade=-1)
self.comb += pll.reset.eq(~platform.request("cpu_reset")) self.comb += pll.reset.eq(~platform.request("cpu_reset"))
pll.register_clkin(platform.request("clk100"), 100e6) pll.register_clkin(platform.request("clk100"), 100e6)
...@@ -94,8 +90,6 @@ class EthernetSoC(BaseSoC): ...@@ -94,8 +90,6 @@ class EthernetSoC(BaseSoC):
self.add_csr("ethmac") self.add_csr("ethmac")
self.add_interrupt("ethmac") self.add_interrupt("ethmac")
self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6)
self.platform.add_false_path_constraints( self.platform.add_false_path_constraints(
......
...@@ -35,12 +35,6 @@ class _CRG(Module): ...@@ -35,12 +35,6 @@ class _CRG(Module):
# # # # # #
self.cd_init.clk.attr.add("keep")
self.cd_por.clk.attr.add("keep")
self.cd_sys.clk.attr.add("keep")
self.cd_sys2x.clk.attr.add("keep")
self.cd_sys2x_i.clk.attr.add("keep")
self.stop = Signal() self.stop = Signal()
# clk / rst # clk / rst
...@@ -124,8 +118,6 @@ class EthernetSoC(BaseSoC): ...@@ -124,8 +118,6 @@ class EthernetSoC(BaseSoC):
self.add_csr("ethmac") self.add_csr("ethmac")
self.add_interrupt("ethmac") self.add_interrupt("ethmac")
self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6)
......
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