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Timothy Pearson
litex-boards
Commits
1ab46562
Commit
1ab46562
authored
4 years ago
by
Skip Hansen
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Take Ethernet PHY out of reset so default clock is 125 Mhz (and baud rate is 115,200)
parent
9b572ece
Changes
2
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2 changed files
with
9 additions
and
0 deletions
+9
-0
litex_boards/platforms/pano_logic_g2.py
litex_boards/platforms/pano_logic_g2.py
+3
-0
litex_boards/targets/pano_logic_g2.py
litex_boards/targets/pano_logic_g2.py
+6
-0
No files found.
litex_boards/platforms/pano_logic_g2.py
100644 → 100755
View file @
1ab46562
...
@@ -97,6 +97,9 @@ _io = [
...
@@ -97,6 +97,9 @@ _io = [
Subsignal
(
"cke"
,
Pins
(
"D2"
),
IOStandard
(
"SSTL18_II"
)),
Subsignal
(
"cke"
,
Pins
(
"D2"
),
IOStandard
(
"SSTL18_II"
)),
Subsignal
(
"odt"
,
Pins
(
"J6"
),
IOStandard
(
"SSTL18_II"
)),
Subsignal
(
"odt"
,
Pins
(
"J6"
),
IOStandard
(
"SSTL18_II"
)),
),
),
# Ethernet phy reset (clk125 is 25 Mhz instead of 125 Mhz if reset is active)
(
"gmii_rst_n"
,
0
,
Pins
(
"R11"
),
IOStandard
(
"LVCMOS33"
)),
]
]
# Platform -----------------------------------------------------------------------------------------
# Platform -----------------------------------------------------------------------------------------
...
...
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litex_boards/targets/pano_logic_g2.py
View file @
1ab46562
...
@@ -46,6 +46,12 @@ class BaseSoC(SoCCore):
...
@@ -46,6 +46,12 @@ class BaseSoC(SoCCore):
sys_clk_freq
=
sys_clk_freq
)
sys_clk_freq
=
sys_clk_freq
)
self
.
add_csr
(
"leds"
)
self
.
add_csr
(
"leds"
)
# Take Ethernet Phy out of reset for SYSCLK of 125 Mhz
gmii_rst_n
=
platform
.
request
(
"gmii_rst_n"
)
self
.
comb
+=
[
gmii_rst_n
.
eq
(
1
)
]
# Build --------------------------------------------------------------------------------------------
# Build --------------------------------------------------------------------------------------------
def
main
():
def
main
():
...
...
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