Commit 1ab46562 authored by Skip Hansen's avatar Skip Hansen
Browse files

Take Ethernet PHY out of reset so default clock is 125 Mhz (and baud rate is 115,200)

parent 9b572ece
...@@ -97,6 +97,9 @@ _io = [ ...@@ -97,6 +97,9 @@ _io = [
Subsignal("cke", Pins("D2"), IOStandard("SSTL18_II")), Subsignal("cke", Pins("D2"), IOStandard("SSTL18_II")),
Subsignal("odt", Pins("J6"), IOStandard("SSTL18_II")), Subsignal("odt", Pins("J6"), IOStandard("SSTL18_II")),
), ),
# Ethernet phy reset (clk125 is 25 Mhz instead of 125 Mhz if reset is active)
("gmii_rst_n", 0, Pins("R11"), IOStandard("LVCMOS33")),
] ]
# Platform ----------------------------------------------------------------------------------------- # Platform -----------------------------------------------------------------------------------------
......
...@@ -46,6 +46,12 @@ class BaseSoC(SoCCore): ...@@ -46,6 +46,12 @@ class BaseSoC(SoCCore):
sys_clk_freq = sys_clk_freq) sys_clk_freq = sys_clk_freq)
self.add_csr("leds") self.add_csr("leds")
# Take Ethernet Phy out of reset for SYSCLK of 125 Mhz
gmii_rst_n = platform.request("gmii_rst_n")
self.comb += [
gmii_rst_n.eq(1)
]
# Build -------------------------------------------------------------------------------------------- # Build --------------------------------------------------------------------------------------------
def main(): def main():
......
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