1. 08 Mar, 2011 2 commits
  2. 28 Feb, 2011 1 commit
  3. 03 Dec, 2010 1 commit
    • Mark Marshall's avatar
      Add support for the Open Graphics Project development card, OGD1, as a SPI flash programmer · 90021f28
      Mark Marshall authored
      The project is in the the process of designing and making a complete,
      open source, graphics card. More info at http://wiki.opengraphics.org
      
      .
      
      The first development card is a PCI add in card containing a couple of
      FPGAs and a couple of serial flash chips (amongst other things). The
      FPGAs are called XP10 and S3 (their part numbers). The XP10 contains its
      own flash and does not need to be programmed by flashrom - it ensures
      that the device can enumerate on the PCI bus without needing further
      configuration.
      
      The larger FPGA is the S3. This is configured from a large SPI flash
      (2 MBytes). The second SPI flash is used to store the VGA BIOS. It is
      smaller (128 KBytes). This patch adds support for programming either of
      the two SPI flash chips.
      
      The programmer device takes one configuration option which selects which
      of the two flash chips is accessed. This must be set to either "cprom"
      or "bprom". (The project refers to the two chips as "cprom" / "bprom",
      "s3" and "bios" are more readable alternatives).
      
      Add support for SST SST25VF010 (REMS). Mark SST SST25VF016B as tested
      for write.
      
      Corresponding to flashrom svn r1241.
      Signed-off-by: default avatarMark Marshall <mark.marshall@csr.com>
      Acked-by: default avatarCarl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
      90021f28
  4. 23 Nov, 2010 1 commit
  5. 13 Oct, 2010 1 commit
  6. 08 Oct, 2010 1 commit
    • Carl-Daniel Hailfinger's avatar
      Move implicit erase out of chip drivers · f52f784b
      Carl-Daniel Hailfinger authored
      
      Flashrom had an implicit erase-on-write for most flash chip and
      programmer drivers, but it was not entirely consistent.
      
      Some drivers had their own hand-rolled partial update functionality
      which made handling partial updates from generic code impossible.
      
      Move implicit erase out of chip drivers, and kill some dead erase
      functions at the same time. A full chip erase is now performed in the
      generic code for all flash chips on write, and after that the whole chip
      is written.
      
      Corresponding to flashrom svn r1206.
      Signed-off-by: default avatarCarl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
      Acked-by: default avatarUwe Hermann <uwe@hermann-uwe.de>
      f52f784b
  7. 15 Sep, 2010 1 commit
    • Carl-Daniel Hailfinger's avatar
      Honor ICH SPI address window for reads · ec489e4e
      Carl-Daniel Hailfinger authored
      
      ICH SPI has the ability to restrict SPI read/write accesses to a given
      address range. The low end of the range is configurable by the BIOS (and
      by flashrom if the BIOS didn't lock down the flash interface), the high
      end of the range is 0xffffff (2^24-1).
      This patch checks for an address range restriction and uses the low end
      of the allowed range as base for SPI reads. A similar workaround for
      REMS/RES opcodes has been committed in r500.
      
      This fixes read on the Intel D945GCLF mainboard where the stock BIOS
      enforces a restricted address range.
      Please note that writes need the same fix, but for architectural reasons
      that fix will be merged once partial write is available.
      
      Corresponding to flashrom svn r1170.
      Signed-off-by: default avatarCarl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
      
      Tested by David Hendricks on the Intel D945GCLF mainboard, results at
      http://paste.flashrom.org/view.php?id=79
      
      Acked-by: default avatarDavid Hendricks <dhendrix@google.com>
      ec489e4e
  8. 03 Sep, 2010 1 commit
    • Idwer Vollering's avatar
      Add Intel Gigabit NIC SPI flashing support · 004f4b79
      Idwer Vollering authored
      
      Tested on a 82541PI (0x8086, 0x107c) using 32-bit hardware.
      
      The last line in nicintel_request_spibus() could be changed so that FL_BUSY
      is used instead.
      
      Shortened sample log:
      [...]
      Found "Intel 82541PI Gigabit Ethernet Controller" (8086:107c, BDF 01:03.0).
      Found chip "ST M25P10.RES" (128 KB, SPI) at physical address 0xfffe0000.
      Multiple flash chips were detected: M25P05.RES M25P10.RES
      Please specify which chip to use with the -c <chipname> option.
      [...]
      
      Corresponding to flashrom svn r1151.
      Signed-off-by: default avatarIdwer Vollering <vidwer@gmail.com>
      Acked-by: default avatarUwe Hermann <uwe@hermann-uwe.de>
      004f4b79
  9. 29 Jul, 2010 1 commit
  10. 28 Jul, 2010 1 commit
    • Carl-Daniel Hailfinger's avatar
      Add Nvidia nForce MCP61/MCP65/MCP67/MCP78S/MCP73/MCP79 SPI flashing support · 2f436168
      Carl-Daniel Hailfinger authored
      
      Huge thanks go to Michael Karcher for reverse engineering the interface
      and to Johannes Sjölund for testing the first iterations of my patch on
      his hardware until it worked.
      
      Thanks to the following testers of the patch:
      * MCP61, 10de:03e0, LPC OK, ECS Geforce6100SM-M, Andrew Cleveland
      * MCP61, 10de:03e0, LPC OK, Biostar NF520-A2 NF61D-A2, Vitaliy Buchynskyy
      * MCP65, 10de:0441, SPI OK, MSI MS-7369 K9N Neo-F v2, Kjell Braden
      * MCP65, 10de:0441, SPI OK, MSI MS-7369, Wolfgang Schnitker
      * MCP65, 10de:0441, SPI OK, MSI MS-7369, Johannes Sjölund
      * MCP65, 10de:0441, SPI OK, MSI MS-7369, Melchior Franz
      * MCP78S, 10de:075c, SPI OK, Asus M3N78 PRO, Brad Rogers
      * MCP78S, 10de:075c, SPI OK, Asus M3N78-VM, Marcel Partap
      * MCP78S, 10de:075c, SPI OK, Asus M4N78 PRO, Kimmo Vuorinen
      * MCP78S, 10de:075c, SPI OK, Asus M4N78 PRO, Vikram Ambrose
      * MCP79, 10de:0aad, SPI OK, Acer Aspire R3600, Andrew Morgan
      * MCP79, 10de:0aae, LPC ??, Lenovo Ideapad S12 laptop, Christian Schmitt
      * MCP79, 10de:0aae, SPI OK, Apple iMac9,1 Mac-F2218EA9, David "dledson"
      
      flashrom will refuse to write/erase for safety reasons if MCP6x/MCP7x
      SPI is detected.
      
      Corresponding to flashrom svn r1113.
      Signed-off-by: default avatarCarl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
      Acked-by: default avatarUwe Hermann <uwe@hermann-uwe.de>
      2f436168
  11. 27 Jul, 2010 1 commit
    • Carl-Daniel Hailfinger's avatar
      Split off programmer.h from flash.h · 5b997c3e
      Carl-Daniel Hailfinger authored
      
      Programmer specific functions are of absolutely no interest to any file
      except those dealing with programmer specific actions (special SPI
      commands and the generic core).
      
      The new header structure is as follows (and yes, improvements are
      possible):
      flashchips.h  flash chip IDs
      chipdrivers.h  chip-specific read/write/... functions
      flash.h  common header for all stuff that doesn't fit elsewhere
      hwaccess.h hardware access functions
      programmer.h  programmer specific functions
      coreboot_tables.h  header from coreboot, internal programmer only
      spi.h SPI command definitions
      
      Corresponding to flashrom svn r1112.
      Signed-off-by: default avatarCarl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
      Acked-by: default avatarUwe Hermann <uwe@hermann-uwe.de>
      5b997c3e
  12. 21 Jul, 2010 1 commit
  13. 14 Jul, 2010 3 commits
  14. 03 Jul, 2010 1 commit
  15. 20 Jun, 2010 2 commits
  16. 31 May, 2010 1 commit
  17. 30 May, 2010 1 commit
  18. 28 May, 2010 1 commit
  19. 26 May, 2010 1 commit
    • Carl-Daniel Hailfinger's avatar
      Handle the following architectures in generic flashrom code · cceafa2a
      Carl-Daniel Hailfinger authored
      
      - x86/x86_64 (little endian)
      - PowerPC (big endian)
      - MIPS (big+little endian)
      
      No changes to programmer specific code. This means any drivers with MMIO
      access will _not_ suddenly start working on big endian systems, but with
      this patch everything is in place to fix them.
      
      Compilation should work on all architectures listed above for all
      drivers except nic3com and nicrealtek which require PCI Port IO which is
      x86-only for now.
      
      To compile without nic3com and nicrealtek, run
      make distclean
      make CONFIG_NIC3COM=no CONFIG_NICREALTEK=no
      
      Thanks to Misha Manulis for testing early versions of this patch on
      PowerPC (big endian) with the satasii programmer.
      Thanks to Segher Boessenkool for design review and for helping out with
      compiler tricks and pointing out that we need eieio on PowerPC.
      Thanks to Vladimir Serbinenko for compile testing on MIPS (little
      endian) and PowerPC (big endian) and for runtime testing on MIPS (little
      endian).
      Thanks to David Daney for compile testing on MIPS (big endian).
      Thanks to Uwe Hermann for compile and runtime testing on x86_64.
      
      DO NOT RUN flashrom ON NON-X86 AFTER APPLYING THIS PATCH!
      This patch only provides the infrastructure, but does not convert any
      drivers, so flashrom will compile, but it won't do the right thing on
      non-x86 platforms.
      
      Corresponding to flashrom svn r1013.
      Signed-off-by: default avatarCarl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
      Acked-by: default avatarMisha Manulis <misha@manulis.com>
      Acked-by: default avatarVladimir 'phcoder/φ-coder' Serbinenko <phcoder@gmail.com>
      Acked-by: default avatarUwe Hermann <uwe@hermann-uwe.de>
      Acked-by: default avatarSegher Boessenkool <segher@kernel.crashing.org>
      cceafa2a
  20. 07 May, 2010 1 commit
  21. 22 Mar, 2010 1 commit
  22. 26 Feb, 2010 1 commit
  23. 12 Feb, 2010 1 commit
  24. 22 Jan, 2010 1 commit
  25. 19 Jan, 2010 2 commits
  26. 12 Jan, 2010 1 commit
  27. 22 Dec, 2009 1 commit
  28. 13 Dec, 2009 1 commit
    • Carl-Daniel Hailfinger's avatar
      Internal (onboard) programming was the only feature which could not be disabled · 66ef4e5f
      Carl-Daniel Hailfinger authored
      Make various pieces of code conditional on support for internal
      programming. Code shared between PCI device programmers and onboard
      programming is now conditional as well.
      
      It is now possible to build only with dummy support:
      make CONFIG_INTERNAL=no CONFIG_NIC3COM=no CONFIG_SATASII=no
      CONFIG_DRKAISER=no CONFIG_SERPROG=no CONFIG_FT2232SPI=no
      
      This allows building for a specific use case only, and it also
      facilitates porting to a new architecture because it is possible to
      focus on highlevel code only.
      
      Note: Either internal or dummy programmer needs to be compiled in due to
      the current behaviour of always picking a default programmer if -p is
      not specified. Picking an arbitrary external programmer as default  
      wouldn't make sense.
      
      Build and runtime tested in all 1024 possible build combinations. The
      only failures are by design as mentioned above.
      
      Corresponding to flashrom svn r797.
      
      Signed-off-by: Carl-Daniel Hailfinger <c-d.h...
      66ef4e5f
  29. 24 Nov, 2009 2 commits
  30. 20 Nov, 2009 1 commit
  31. 16 Nov, 2009 1 commit
  32. 01 Oct, 2009 1 commit
  33. 18 Sep, 2009 1 commit
  34. 16 Sep, 2009 1 commit