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The SST39LF series has the same IDs. Add short AMIC vendor ID to
flashrom.

Corresponding to flashrom svn r225 and coreboot v2 svn r3299.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>

This paves the way to have a fully generic generic_spi_command without
knowledge about any SPI controller.

The third step would be calling SPI controller functions via a function
pointer.

Corresponding to flashrom svn r224 and coreboot v2 svn r3296.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>

This is a very early step toward cleaning up SPI code in flashrom.

Corresponding to flashrom svn r223 and coreboot v2 svn r3295.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

Currently there is an ongoing technology migration from LPC/FWH to SPI chips.
For this reason some boards have multiple chips of different technologies
onboard. This patch makes flashrom probe for up to 3 chips and if more than
one chip is found flashrom exits, asking the user to specify -c.

[root@localhost src]# ./flashrom
...
Multiple flash chips were detected: SST49LF008A M25P16@ICH9
Please specify which chip to use with the -c <chipname> option.
[root@localhost src]# 

Corresponding to flashrom svn r222 and coreboot v2 svn r3291.
Signed-off-by: Claus Gindhart <claus.gindhart@kontron.com>
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Claus Gindhart <claus.gindhart@kontron.com>

Two bits indicate OK and BAD for each operation PROBE READ ERASE WRITE.
8 bits out of 32 are in use now. No bits set means nothing has been tested.
For chips with at least one operation that is not tested or not working, the
user is asked to email a report to a special email adress so that the table
can be updated.

All chips are TEST_UNTESTED for now.

Corresponding to flashrom svn r221 and coreboot v2 svn r3277.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

Corresponding to flashrom svn r220 and coreboot v2 svn r3275.
Signed-off-by: Bari Ari <bari@onelabs.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>

The generic jedec.c does not work for the ST M50FLW flash devices,
because they need an unlock command first. For this reason, ST M50FLW
support is moved to a new HW support module, because any change in
jedec.c would bear the risk to cause problems with the already supported
devices.

It's already tested with ST M50FLW080A; the other chips of this family i
dont have available, so i couldnt test it.

Corresponding to flashrom svn r219 and coreboot v2 svn r3274.
Signed-off-by: Claus Gindhart <claus.gindhart@kontron.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>

The read pointer was already checked properly.

Corresponding to flashrom svn r218 and coreboot v2 svn r3273.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>

Flash pages, which where excluded from updating using the exclude or the
layout option, as well as areas, whose flash contents already contain
the desired data, will be skipped. These ensures absolute data security
of critical areas (BIOS boot block), e.g. against a sudden power off or
a CPU hangup during flashing. As a nice side effect, it speeds up the
flash process, if the BIOS to be flashed is very similar to the version
in flash.

Corresponding to flashrom svn r217 and coreboot v2 svn r3260.
Signed-off-by: Claus Gindhart <claus.gindhart@kontron.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>

Corresponding to flashrom svn r216 and coreboot v2 svn r3221.
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Joseph Smith <joe@smittys.pointclark.net>

Straight from the datasheet, untested.

Corresponding to flashrom svn r215 and coreboot v2 svn r3167.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>

Forgot to add the file.

Support for the Winbond W39V080FA series of chips. Support for flashing
on the Kontron 986LCD-M board.

Corresponding to flashrom svn r214 and coreboot v2 svn r3166.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

Support for flashing on the Kontron 986LCD-M board.

Corresponding to flashrom svn r213 and coreboot v2 svn r3165.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

Corresponding to flashrom svn r212 and coreboot v2 svn r3153.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>

Corresponding to flashrom svn r211 and coreboot v2 svn r3152.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>

Corresponding to flashrom svn r210 and coreboot v2 svn r3151.

mechanism.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>

Corresponding to flashrom svn r209 and coreboot v2 svn r3146.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>

This fixes the problem of not being able to erase the chip.

Corresponding to flashrom svn r208 and coreboot v2 svn r3145.
Signed-off-by: Joseph Smith <joe@smittys.pointclark.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

Functionality (except printing) should be unchanged.

Corresponding to flashrom svn r207 and coreboot v2 svn r3144.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

Ward says:
This code detects the ICH8 chipset on my laptop, and it appears to use
SPI.
Acked-by: Ward Vandewege <ward@gnu.org>

Corresponding to flashrom svn r206 and coreboot v2 svn r3142.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>

Corresponding to flashrom svn r205 and coreboot v2 svn r3141.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

Corresponding to flashrom svn r204 and coreboot v2 svn r3140.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

Cosmetic changes in some files, partly bending the 80-characters-per-line
rule in this special case, as the 80-character-limited version looks
equally crappy even in an 80x25 console/xterm, so let's make it at least
look good in a high-resolution xterm.

Corresponding to flashrom svn r203 and coreboot v2 svn r3139.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>

Corresponding to flashrom svn r202 and coreboot v2 svn r3138.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>

Corresponding to flashrom svn r201 and coreboot v2 svn r3137.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>

It's just an example, likely never been used in the last few years, and
the contents are available in the README already anyway.

Corresponding to flashrom svn r200 and coreboot v2 svn r3134.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Ward Vandewege <ward@gnu.org>

Corresponding to flashrom svn r199 and coreboot v2 svn r3133.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Ward Vandewege <ward@gnu.org>

The file was written by Stefan Reinauer for coresystems GmbH in 2005, as
confirmed on IRC.

Corresponding to flashrom svn r198 and coreboot v2 svn r3126.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>

Also add a comment about NULL subsystem IDs leaving the board entry out
of auto-detection logic.

Corresponding to flashrom svn r197 and coreboot v2 svn r3110.
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Stefan Reinauer <stepan@coresystems.de>

With this small change it is possible to build flashrom again when
specifying custom CFLAGS/LDFLAGS from the make command line like.

  make CFLAGS="..." LDFLAGS="..."

I need to do this when building flashrom in a cross compiler environment
like buildroot for a foreign target.

Corresponding to flashrom svn r196 and coreboot v2 svn r3102.
Signed-off-by: Clark Rawlins <clark@bit63.org>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>

 - Remove the "enable write to flash" message, as the caller appears to
   already report that.

 - Move the 'modprobe msr' suggestions to the first lseek64 error handling, as
   we get an error there already.

 - Rename a perror string from "read" to "read msr", as we use the latter
   already in this function for another read.

Corresponding to flashrom svn r195 and coreboot v2 svn r3101.
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>

Corresponding to flashrom svn r194 and coreboot v2 svn r3099.
Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>

Also, move a big code comment to the top of enable_flash_cs5536().

Corresponding to flashrom svn r193 and coreboot v2 svn r3098.
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>

This implements support for devices using AMD Geode companion chip
CS5536 that have the Boot ROM on NOR flash that is directly connected to
FLASH_CS3 (Boot Flash Chip Select). We need to write enable it in the
NORF_CTL MSR register for flashrom to be able to write to it, including
JEDEC probe commands.

This patch allows us to stop using AMD gx_utils.ko for BIOS flashing on
the DBE61.

Corresponding to flashrom svn r192 and coreboot v2 svn r3097.
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>

Some vendors like Programmable Micro Corp (PMC) need this. Both the
serial and parallel flash JEDEC detection routines would benefit from a
parity/sanity check of the vendor ID. Will do this later.

Add support for the PMC Pm25LV family of SPI flash chips.

Corresponding to flashrom svn r191 and coreboot v2 svn r3091.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Chris Lingard  <chris@stockwith.co.uk>

Make the vendor name optional in the -m flashrom parameter when there's only one board name that matches

The full syntax still works, and is required when two vendors have
boards with the same names.

Corresponding to flashrom svn r190 and coreboot v2 svn r3082.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>

Corresponding to flashrom svn r189 and coreboot v2 svn r3080.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>

Corresponding to flashrom svn r188 and coreboot v2 svn r3078.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>

Tested on the pcengines alix1c and works fine.
Acked-by: Ronald G. Minnich <rminnich@gmail.com>

Corresponding to flashrom svn r187 and coreboot v2 svn r3074.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

I've tested and verified the chip myself, and it seems to work
everything like supposted, since Carl-Daniel has patched flashrom to
use the read funktion on verifying. 

"benchvice flashrom # ./flashrom -m gigabyte:m57sli -v test.4mb
Calibrating delay loop... OK.
No coreboot table found.
Found chipset "NVIDIA MCP55", enabling flash write... OK.
Found board "GIGABYTE GA-M57SLI-S4": enabling flash write... 
Serial flash segment 0xfffe0000-0xffffffff enabled
Serial flash segment 0x000e0000-0x000fffff enabled
Serial flash segment 0xffee0000-0xffefffff disabled
Serial flash segment 0xfff80000-0xfffeffff enabled
LPC write to serial flash enabled
serial flash pin 29
OK.
MX25L3205 found at physical address 0xffc00000.
Flash part is MX25L3205 (4096 KB).
Flash image seems to be a legacy BIOS. Disabling checks.
Verifying flash... VERIFIED.
benchvice flashrom # ls -l test.4mb
-rw-r--r-- 1 root root 4194304 22. Jan 16:27 test.4mb

Corresponding to flashrom svn r186 and coreboot v2 svn r3072.
Signed-off-by: Harald Gutmann <harald.gutmann@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>