Initial import of ADS7950 ADC driver

tercelspi/tercelspi.py

@@ -166,3 +166,100 @@ class TercelSPI(Module, AutoCSR):
         vdir = get_data_mod("peripheral", "tercelspi").data_location
         platform.add_source(os.path.join(vdir, "wishbone_spi_master.v"))
         platform.add_source(os.path.join(vdir, "phy.v"))
+
+# ADS7950 interface --------------------------------------------------------------------------------
+
+class ADS7950Driver(Module, AutoCSR):
+    def __init__(self, platform, pads, clk_freq, endianness="big", adr_offset=0x0, lattice_ecp5_usrmclk=False, debug_signals=None):
+        self.bus     = bus     = wishbone.Interface(data_width=32, adr_width=30)
+        self.cs_n    = cs_n    = Signal()
+
+        # Bus endianness handlers
+        self.dat_w = Signal(32)
+        self.dat_r = Signal(32)
+        self.comb += self.dat_w.eq(bus.dat_w if endianness == "big" else reverse_bytes(bus.dat_w))
+        self.comb += bus.dat_r.eq(self.dat_r if endianness == "big" else reverse_bytes(self.dat_r))
+
+        # SPI bus signals
+        self.spi_clock = Signal()
+        self.spi_d0_out = Signal()
+        self.spi_d0_direction = Signal()
+        self.spi_d0_in = Signal()
+        self.spi_d1_out = Signal()
+        self.spi_d1_direction = Signal()
+        self.spi_d1_in = Signal()
+        self.spi_ss_n = Signal()
+
+        # Debug signals
+        self.debug_port = Signal(8)
+
+        self.specials += Instance("ads7950_spi_driver_wishbone",
+            # Configuration data
+            i_sys_clk_freq = clk_freq,
+
+            # Wishbone signals
+            i_wb_cyc = bus.cyc,
+            i_wb_stb = bus.stb,
+            i_wb_we = bus.we,
+            i_wb_addr = bus.adr,
+            i_wb_dat_w = self.dat_w,
+            o_wb_dat_r = self.dat_r,
+            i_wb_sel = bus.sel,
+            o_wb_ack = bus.ack,
+            o_wb_err = bus.err,
+
+            # Clock and reset
+            # Put the peripheral on the both main system clock and reset domains
+            i_peripheral_reset = ResetSignal('sys'),
+            i_peripheral_clock = ClockSignal('sys'),
+
+            # Debug port
+            o_debug_port = self.debug_port,
+
+            # SPI interface
+            o_spi_clock = self.spi_clock,
+            o_spi_d0_out = self.spi_d0_out,
+            o_spi_d0_direction = self.spi_d0_direction,
+            i_spi_d0_in = self.spi_d0_in,
+            o_spi_d1_out = self.spi_d1_out,
+            o_spi_d1_direction = self.spi_d1_direction,
+            i_spi_d1_in = self.spi_d1_in,
+            o_spi_ss_n = self.spi_ss_n
+        )
+        # Add Verilog source files
+        self.add_sources(platform)
+
+        # I/O drivers
+        self.specials += SDRTristate(
+            io = pads.dq[0],
+            o  = self.spi_d0_out,
+            oe = self.spi_d0_direction,
+            i  = self.spi_d0_in,
+        )
+        self.specials += SDRTristate(
+            io = pads.dq[1],
+            o  = self.spi_d1_out,
+            oe = self.spi_d1_direction,
+            i  = self.spi_d1_in,
+        )
+        self.comb += pads.cs_n.eq(self.spi_ss_n)
+        if lattice_ecp5_usrmclk:
+            self.specials += Instance("USRMCLK",
+                i_USRMCLKI  = self.spi_clock,
+                i_USRMCLKTS = 0
+            )
+        else:
+            self.comb += pads.clk.eq(self.spi_clock)
+
+        if debug_signals is not None:
+            self.comb += debug_signals[0].eq(self.spi_d0_in)
+            self.comb += debug_signals[1].eq(self.spi_d1_in)
+            #self.comb += debug_signals[2].eq(self.debug_port[0])
+            #self.comb += debug_signals[3].eq(self.debug_port[1])
+
+
+    @staticmethod
+    def add_sources(platform):
+        vdir = get_data_mod("peripheral", "tercelspi").data_location
+        platform.add_source(os.path.join(vdir, "wishbone_ads7950_spi_driver.v"))
+        platform.add_source(os.path.join(vdir, "phy.v"))