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Kestrel Collaboration
Kestrel LiteX
pythondata-peripheral-opencores1wire
Commits
4eb366ac
Commit
4eb366ac
authored
2 years ago
by
Raptor Engineering Development Team
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Increase clock divider register width to 16 bits in 8 bit bus mode
parent
1016efb6
Changes
1
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18 additions
and
10 deletions
+18
-10
pythondata_peripheral_opencores1wire/rtl/third_party/onewire_master/sockit_owm.v
...pencores1wire/rtl/third_party/onewire_master/sockit_owm.v
+18
-10
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pythondata_peripheral_opencores1wire/rtl/third_party/onewire_master/sockit_owm.v
View file @
4eb366ac
...
...
@@ -113,7 +113,7 @@ module sockit_owm #(
localparam
PDW
=
(
BDW
==
32
)
?
24
:
8
;
// size of boudrate generator counter (divider for normal mode is largest)
localparam
CDW
=
CDR_E
?
((
BDW
==
32
)
?
16
:
8
)
:
$
clog2
(
CDR_N
);
localparam
CDW
=
CDR_E
?
((
BDW
==
32
)
?
16
:
16
)
:
$
clog2
(
CDR_N
);
// size of port select signal
localparam
SDW
=
$
clog2
(
OWN
);
...
...
@@ -132,6 +132,8 @@ wire bus_wen_ctl_sts;
wire
bus_wen_pwr_sel
;
wire
bus_wen_cdr_n
;
wire
bus_wen_cdr_o
;
wire
bus_wen_cdr_n_high
;
wire
bus_wen_cdr_o_high
;
// read data bus segments
wire
[
7
:
0
]
bus_rdt_ctl_sts
;
...
...
@@ -264,8 +266,10 @@ end else if (BDW==8) begin
5'b01111
:
bus_rdt
=
sys_clk_freq
[
31
:
24
];
5'b10000
:
bus_rdt
=
bus_rdt_ctl_sts
;
5'b10001
:
bus_rdt
=
bus_rdt_pwr_sel
;
5'b10010
:
bus_rdt
=
cdr_n
;
5'b10011
:
bus_rdt
=
cdr_o
;
5'b10010
:
bus_rdt
=
cdr_n
[
7
:
0
];
5'b10011
:
bus_rdt
=
cdr_n
[
15
:
8
];
5'b10100
:
bus_rdt
=
cdr_o
[
7
:
0
];
5'b10101
:
bus_rdt
=
cdr_o
[
15
:
8
];
default:
bus_rdt
=
8'h00
;
endcase
end
...
...
@@ -283,11 +287,13 @@ generate if (BDW==32) begin
assign
bus_wen_cdr_n
=
bus_wen
&
bus_adr
==
3'b101
;
assign
bus_wen_cdr_o
=
bus_wen
&
bus_adr
==
3'b101
;
end
else
if
(
BDW
==
8
)
begin
assign
bus_ren_ctl_sts
=
bus_ren
&
bus_adr
[
4
:
0
]
==
5'b10000
;
assign
bus_wen_ctl_sts
=
bus_wen
&
bus_adr
[
4
:
0
]
==
5'b10000
;
assign
bus_wen_pwr_sel
=
bus_wen
&
bus_adr
[
4
:
0
]
==
5'b10001
;
assign
bus_wen_cdr_n
=
bus_wen
&
bus_adr
[
4
:
0
]
==
5'b10010
;
assign
bus_wen_cdr_o
=
bus_wen
&
bus_adr
[
4
:
0
]
==
5'b10011
;
assign
bus_ren_ctl_sts
=
bus_ren
&
bus_adr
[
4
:
0
]
==
5'b10000
;
assign
bus_wen_ctl_sts
=
bus_wen
&
bus_adr
[
4
:
0
]
==
5'b10000
;
assign
bus_wen_pwr_sel
=
bus_wen
&
bus_adr
[
4
:
0
]
==
5'b10001
;
assign
bus_wen_cdr_n
=
bus_wen
&
bus_adr
[
4
:
0
]
==
5'b10010
;
assign
bus_wen_cdr_n_high
=
bus_wen
&
bus_adr
[
4
:
0
]
==
5'b10011
;
assign
bus_wen_cdr_o
=
bus_wen
&
bus_adr
[
4
:
0
]
==
5'b10100
;
assign
bus_wen_cdr_o_high
=
bus_wen
&
bus_adr
[
4
:
0
]
==
5'b10101
;
end
endgenerate
//////////////////////////////////////////////////////////////////////////////
...
...
@@ -312,8 +318,10 @@ generate
cdr_n
<=
CDR_N
;
cdr_o
<=
CDR_O
;
end
else
begin
if
(
bus_wen_cdr_n
)
cdr_n
<=
bus_wdt
;
if
(
bus_wen_cdr_o
)
cdr_o
<=
bus_wdt
;
if
(
bus_wen_cdr_n
)
cdr_n
[
7
:
0
]
<=
bus_wdt
;
if
(
bus_wen_cdr_n_high
)
cdr_n
[
15
:
8
]
<=
bus_wdt
;
if
(
bus_wen_cdr_o
)
cdr_o
[
7
:
0
]
<=
bus_wdt
;
if
(
bus_wen_cdr_o_high
)
cdr_o
[
15
:
8
]
<=
bus_wdt
;
end
end
end
else
begin
...
...
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