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Kestrel Collaboration
Kestrel LiteX
migen
Commits
ecce6f59
Commit
ecce6f59
authored
6 years ago
by
Sebastien Bourdeauducq
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sayma: use clock-capable Ethernet RX clock pin (requires board rework)
parent
b1943a3c
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migen/build/platforms/sinara/sayma_amc.py
migen/build/platforms/sinara/sayma_amc.py
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migen/build/platforms/sinara/sayma_amc.py
View file @
ecce6f59
...
...
@@ -126,7 +126,7 @@ _io = [
(
"eth_clocks"
,
0
,
Subsignal
(
"tx"
,
Pins
(
"M22"
)),
Subsignal
(
"rx"
,
Pins
(
"
T25
"
)),
Subsignal
(
"rx"
,
Pins
(
"
AG11
"
)),
IOStandard
(
"LVCMOS33"
)
),
(
"eth_mii"
,
0
,
...
...
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