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Kestrel Collaboration
Kestrel LiteX
migen
Commits
e9be3241
Commit
e9be3241
authored
12 years ago
by
Sebastien Bourdeauducq
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Fix instance support
parent
e4f531a7
Changes
3
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Showing
3 changed files
with
11 additions
and
8 deletions
+11
-8
migen/fhdl/structure.py
migen/fhdl/structure.py
+3
-3
migen/fhdl/tools.py
migen/fhdl/tools.py
+6
-3
migen/fhdl/verilog.py
migen/fhdl/verilog.py
+2
-2
No files found.
migen/fhdl/structure.py
View file @
e9be3241
...
@@ -209,14 +209,14 @@ class Instance:
...
@@ -209,14 +209,14 @@ class Instance:
def
__init__
(
self
,
of
,
outs
=
[],
ins
=
[],
parameters
=
[],
clkport
=
""
,
rstport
=
""
,
name
=
""
):
def
__init__
(
self
,
of
,
outs
=
[],
ins
=
[],
parameters
=
[],
clkport
=
""
,
rstport
=
""
,
name
=
""
):
self
.
of
=
of
self
.
of
=
of
if
name
:
if
name
:
self
.
name
=
name
self
.
name
_override
=
name
else
:
else
:
self
.
name
=
of
self
.
name
_override
=
of
def
process_io
(
x
):
def
process_io
(
x
):
if
isinstance
(
x
[
1
],
Signal
):
if
isinstance
(
x
[
1
],
Signal
):
return
x
# override
return
x
# override
elif
isinstance
(
x
[
1
],
BV
):
elif
isinstance
(
x
[
1
],
BV
):
return
(
x
[
0
],
Signal
(
x
[
1
],
self
.
name
+
"_"
+
x
[
0
]))
return
(
x
[
0
],
Signal
(
x
[
1
],
self
.
name
_override
+
"_"
+
x
[
0
]))
else
:
else
:
raise
TypeError
raise
TypeError
self
.
outs
=
dict
(
map
(
process_io
,
outs
))
self
.
outs
=
dict
(
map
(
process_io
,
outs
))
...
...
This diff is collapsed.
Click to expand it.
migen/fhdl/tools.py
View file @
e9be3241
...
@@ -73,13 +73,16 @@ def group_by_targets(sl):
...
@@ -73,13 +73,16 @@ def group_by_targets(sl):
groups
.
append
((
targets
,
[
statement
]))
groups
.
append
((
targets
,
[
statement
]))
return
groups
return
groups
def
list_inst_outs
(
i
):
def
list_inst_
ios
(
i
,
ins
,
outs
):
if
isinstance
(
i
,
Fragment
):
if
isinstance
(
i
,
Fragment
):
return
list_inst_o
ut
s
(
i
.
instances
)
return
list_inst_
i
os
(
i
.
instances
,
ins
,
outs
)
else
:
else
:
l
=
[]
l
=
[]
for
x
in
i
:
for
x
in
i
:
l
+=
list
(
map
(
lambda
x
:
x
[
1
],
list
(
x
.
outs
.
items
())))
if
ins
:
l
+=
x
.
ins
.
values
()
if
outs
:
l
+=
x
.
outs
.
values
()
return
set
(
l
)
return
set
(
l
)
def
is_variable
(
node
):
def
is_variable
(
node
):
...
...
This diff is collapsed.
Click to expand it.
migen/fhdl/verilog.py
View file @
e9be3241
...
@@ -98,7 +98,7 @@ def _list_comb_wires(f):
...
@@ -98,7 +98,7 @@ def _list_comb_wires(f):
def
_printheader
(
f
,
ios
,
name
,
ns
):
def
_printheader
(
f
,
ios
,
name
,
ns
):
sigs
=
list_signals
(
f
)
sigs
=
list_signals
(
f
)
targets
=
list_targets
(
f
)
targets
=
list_targets
(
f
)
instouts
=
list_inst_
outs
(
f
)
instouts
=
list_inst_
ios
(
f
,
False
,
True
)
wires
=
_list_comb_wires
(
f
)
wires
=
_list_comb_wires
(
f
)
r
=
"module "
+
name
+
"(
\n
"
r
=
"module "
+
name
+
"(
\n
"
firstp
=
True
firstp
=
True
...
@@ -213,7 +213,7 @@ def convert(f, ios=set(), name="top", clk_signal=None, rst_signal=None, return_n
...
@@ -213,7 +213,7 @@ def convert(f, ios=set(), name="top", clk_signal=None, rst_signal=None, return_n
if
rst_signal
is
None
:
if
rst_signal
is
None
:
rst_signal
=
Signal
(
name_override
=
"sys_rst"
)
rst_signal
=
Signal
(
name_override
=
"sys_rst"
)
ios
.
add
(
rst_signal
)
ios
.
add
(
rst_signal
)
ns
=
build_namespace
(
list_signals
(
f
)
|
ios
)
ns
=
build_namespace
(
list_signals
(
f
)
|
list_inst_ios
(
f
,
True
,
True
)
|
ios
)
ios
|=
f
.
pads
ios
|=
f
.
pads
...
...
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Click to expand it.
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