Commit e11d9b93 authored by Sebastien Bourdeauducq's avatar Sebastien Bourdeauducq
Browse files

bus/wishbone2asmi: cache hits working

parent 1662e1b3
...@@ -61,15 +61,15 @@ class WB2ASMI: ...@@ -61,15 +61,15 @@ class WB2ASMI:
data_we.eq(Replicate(1, adw//8)) data_we.eq(Replicate(1, adw//8))
).Else( ).Else(
data_di.eq(Replicate(self.wishbone.dat_i, adw//32)), data_di.eq(Replicate(self.wishbone.dat_i, adw//32)),
If(self.wishbone.cyc_i & self.wishbone.stb_i & self.wishbone.ack_o, If(self.wishbone.cyc_i & self.wishbone.stb_i & self.wishbone.we_i & self.wishbone.ack_o,
displacer(self.wishbone.we_i, adr_offset, data_we, 2**offsetbits) displacer(self.wishbone.sel_i, adr_offset, data_we, 2**offsetbits, reverse=True)
) )
), ),
If(write_to_asmi, If(write_to_asmi,
self.asmiport.dat_w.eq(data_do), self.asmiport.dat_w.eq(data_do),
self.asmiport.dat_wm.eq(Replicate(1, adw//8)) self.asmiport.dat_wm.eq(Replicate(1, adw//8))
), ),
chooser(data_do, adr_offset_r, self.wishbone.dat_o) chooser(data_do, adr_offset_r, self.wishbone.dat_o, reverse=True)
] ]
sync += [ sync += [
adr_offset_r.eq(adr_offset) adr_offset_r.eq(adr_offset)
......
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