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Kestrel Collaboration
Kestrel LiteX
migen
Commits
e0d7a23a
Commit
e0d7a23a
authored
7 years ago
by
Florent Kermarrec
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build/platforms: add initial sayma_amc platform (clk50, leds, serial, ddram_32 and ddram_64)
parent
ea55abca
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migen/build/platforms/sayma_amc.py
migen/build/platforms/sayma_amc.py
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migen/build/platforms/sayma_amc.py
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e0d7a23a
from
migen.build.generic_platform
import
*
from
migen.build.xilinx
import
XilinxPlatform
_io
=
[
(
"user_led"
,
0
,
Pins
(
"AG9"
),
IOStandard
(
"LVCMOS18"
)),
# sfp1_led1
(
"user_led"
,
1
,
Pins
(
"AJ10"
),
IOStandard
(
"LVCMOS18"
)),
# sfp1_led2
(
"user_led"
,
2
,
Pins
(
"AJ13"
),
IOStandard
(
"LVCMOS18"
)),
# sfp2_led1
(
"user_led"
,
3
,
Pins
(
"AE13"
),
IOStandard
(
"LVCMOS18"
)),
# sfp2_led2
(
"clk50"
,
0
,
Pins
(
"AF9"
),
IOStandard
(
"LVCMOS18"
)),
(
"serial"
,
0
,
Subsignal
(
"tx"
,
Pins
(
"AK8"
)),
Subsignal
(
"rx"
,
Pins
(
"AL8"
)),
IOStandard
(
"LVCMOS18"
)
),
(
"ddram_32"
,
1
,
Subsignal
(
"a"
,
Pins
(
"E15 D15 J16 K18 H16 K17 K16 J15"
,
"K15 D14 D18 G15 L18 G14 L15"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"ba"
,
Pins
(
"L19 H17 G16"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"ras_n"
,
Pins
(
"E18"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"cas_n"
,
Pins
(
"E16"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"we_n"
,
Pins
(
"D16"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"cs_n"
,
Pins
(
"G19"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"dm"
,
Pins
(
"F27 E26 D23 G24"
),
IOStandard
(
"SSTL15"
),
Misc
(
"DATA_RATE=DDR"
)),
Subsignal
(
"dq"
,
Pins
(
"C28 B27 A27 C27 D28 E28 A28 D29"
,
"D25 C26 E25 B25 C24 A25 D24 B26"
,
"B20 D21 B22 E23 E22 D20 B21 A20"
,
"F23 H21 F24 G21 F22 E21 G22 E20"
),
IOStandard
(
"SSTL15_DCI"
),
Misc
(
"ODT=RTT_40"
),
Misc
(
"DATA_RATE=DDR"
)),
Subsignal
(
"dqs_p"
,
Pins
(
"B29 B24 C21 G20"
),
IOStandard
(
"DIFF_SSTL15"
),
Misc
(
"DATA_RATE=DDR"
)),
Subsignal
(
"dqs_n"
,
Pins
(
"A29 A24 C22 F20"
),
IOStandard
(
"DIFF_SSTL15"
),
Misc
(
"DATA_RATE=DDR"
)),
Subsignal
(
"clk_p"
,
Pins
(
"J19"
),
IOStandard
(
"DIFF_SSTL15"
),
Misc
(
"DATA_RATE=DDR"
)),
Subsignal
(
"clk_n"
,
Pins
(
"J18"
),
IOStandard
(
"DIFF_SSTL15"
),
Misc
(
"DATA_RATE=DDR"
)),
Subsignal
(
"cke"
,
Pins
(
"H18"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"odt"
,
Pins
(
"F19"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"reset_n"
,
Pins
(
"F14"
),
IOStandard
(
"LVCMOS15"
)),
Misc
(
"SLEW=FAST"
),
),
(
"ddram_64"
,
0
,
Subsignal
(
"a"
,
Pins
(
"AE17 AL17 AG16 AG17 AD16 AH14 AD15 AK15"
,
"AF14 AF15 AL18 AL15 AE18 AJ15 AG14"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"ba"
,
Pins
(
"AF17 AD19 AD18"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"ras_n"
,
Pins
(
"AH19"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"cas_n"
,
Pins
(
"AK18"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"we_n"
,
Pins
(
"AG19"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"cs_n"
,
Pins
(
"AF18"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"dm"
,
Pins
(
"AD21 AE25 AJ21 AM21 AH26 AN26 AJ29 AL32"
),
IOStandard
(
"SSTL15"
),
Misc
(
"DATA_RATE=DDR"
)),
Subsignal
(
"dq"
,
Pins
(
"AE23 AG20 AF22 AF20 AE22 AD20 AG22 AE20"
,
"AJ24 AG24 AJ23 AF23 AH23 AF24 AH22 AG25"
,
"AL22 AL25 AM20 AK23 AK22 AL24 AL20 AL23"
,
"AM24 AN23 AN24 AP23 AP25 AN22 AP24 AM22"
,
"AH28 AK26 AK28 AM27 AJ28 AH27 AK27 AM26"
,
"AL30 AP29 AM30 AN28 AL29 AP28 AM29 AN27"
,
"AH31 AH32 AJ34 AK31 AJ31 AJ30 AH34 AK32"
,
"AN33 AP33 AM34 AP31 AM32 AN31 AL34 AN32"
),
IOStandard
(
"SSTL15_DCI"
),
Misc
(
"ODT=RTT_40"
),
Misc
(
"DATA_RATE=DDR"
)),
Subsignal
(
"dqs_p"
,
Pins
(
"AG21 AH24 AJ20 AP20 AL27 AN29 AH33 AN34"
),
IOStandard
(
"DIFF_SSTL15"
),
Misc
(
"DATA_RATE=DDR"
)),
Subsignal
(
"dqs_n"
,
Pins
(
"AH21 AJ25 AK20 AP21 AL28 AP30 AJ33 AP34"
),
IOStandard
(
"DIFF_SSTL15"
),
Misc
(
"DATA_RATE=DDR"
)),
Subsignal
(
"clk_p"
,
Pins
(
"AE16"
),
IOStandard
(
"DIFF_SSTL15"
),
Misc
(
"DATA_RATE=DDR"
)),
Subsignal
(
"clk_n"
,
Pins
(
"AE15"
),
IOStandard
(
"DIFF_SSTL15"
),
Misc
(
"DATA_RATE=DDR"
)),
Subsignal
(
"cke"
,
Pins
(
"AL19"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"odt"
,
Pins
(
"AJ18"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"reset_n"
,
Pins
(
"AJ14"
),
IOStandard
(
"LVCMOS15"
)),
Misc
(
"SLEW=FAST"
),
),
]
class
Platform
(
XilinxPlatform
):
default_clk_name
=
"clk50"
default_clk_period
=
20.0
def
__init__
(
self
):
XilinxPlatform
.
__init__
(
self
,
"xcku040-ffva1156-2-e"
,
_io
,
toolchain
=
"vivado"
)
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