Commit ddf52811 authored by Sebastien Bourdeauducq's avatar Sebastien Bourdeauducq
Browse files

xilinx: fix Ultrascale IDDRE1 pin names

parent 714c79e5
...@@ -202,10 +202,10 @@ class XilinxDDRInputImplKU(Module): ...@@ -202,10 +202,10 @@ class XilinxDDRInputImplKU(Module):
self.specials += Instance("IDDRE1", self.specials += Instance("IDDRE1",
p_DDR_CLK_EDGE="SAME_EDGE_PIPELINED", p_DDR_CLK_EDGE="SAME_EDGE_PIPELINED",
p_IS_C_INVERTED=0, p_IS_C_INVERTED=0,
i_d=i, i_D=i,
o_q1=o1, o_q2=o2, o_Q1=o1, o_Q2=o2,
i_c=clk, i_cb=~clk, i_C=clk, i_CB=~clk,
i_r=0 i_R=0
) )
......
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