Skip to content
GitLab
Projects
Groups
Snippets
Help
Loading...
Help
Help
Support
Community forum
Keyboard shortcuts
?
Submit feedback
Contribute to GitLab
Sign in / Register
Toggle navigation
Open sidebar
Kestrel Collaboration
Kestrel LiteX
migen
Commits
ddf52811
Commit
ddf52811
authored
7 years ago
by
Sebastien Bourdeauducq
Browse files
Options
Download
Email Patches
Plain Diff
xilinx: fix Ultrascale IDDRE1 pin names
parent
714c79e5
Changes
1
Hide whitespace changes
Inline
Side-by-side
Showing
1 changed file
with
4 additions
and
4 deletions
+4
-4
migen/build/xilinx/common.py
migen/build/xilinx/common.py
+4
-4
No files found.
migen/build/xilinx/common.py
View file @
ddf52811
...
@@ -202,10 +202,10 @@ class XilinxDDRInputImplKU(Module):
...
@@ -202,10 +202,10 @@ class XilinxDDRInputImplKU(Module):
self
.
specials
+=
Instance
(
"IDDRE1"
,
self
.
specials
+=
Instance
(
"IDDRE1"
,
p_DDR_CLK_EDGE
=
"SAME_EDGE_PIPELINED"
,
p_DDR_CLK_EDGE
=
"SAME_EDGE_PIPELINED"
,
p_IS_C_INVERTED
=
0
,
p_IS_C_INVERTED
=
0
,
i_
d
=
i
,
i_
D
=
i
,
o_
q
1
=
o1
,
o_
q
2
=
o2
,
o_
Q
1
=
o1
,
o_
Q
2
=
o2
,
i_
c
=
clk
,
i_
cb
=~
clk
,
i_
C
=
clk
,
i_
CB
=~
clk
,
i_
r
=
0
i_
R
=
0
)
)
...
...
This diff is collapsed.
Click to expand it.
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
.
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment