Commit dc724f9e authored by Fabien Marteau's avatar Fabien Marteau Committed by Sebastien Bourdeauducq
Browse files

migen/genlib: little module documentation

Signed-off-by: default avatarFabien Marteau <fabien.marteau@armadeus.com>
parent 7cb36347
"""
Clock domain crossing module
"""
from migen.fhdl.structure import *
from migen.fhdl.module import Module
from migen.fhdl.specials import Special
......
......@@ -38,6 +38,8 @@ class DifferentialOutput(Special):
class CRG(Module):
""" Clock and Reset Generator """
def __init__(self, clk, rst=0):
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_por = ClockDomain(reset_less=True)
......
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