Commit c79d9888 authored by whitequark's avatar whitequark
Browse files

build/platforms/versaecp55g: add X3 external connector.

parent d60cea0b
...@@ -72,12 +72,59 @@ _io = [ ...@@ -72,12 +72,59 @@ _io = [
] ]
_connectors = [
("X3",
"None", # (no pin 0)
"None", # 1 GND
"None", # 2 N/C
"None", # 3 +2V5
"B19", # 4 EXPCON_IO29
"B12", # 5 EXPCON_IO30
"B9", # 6 EXPCON_IO31
"E6", # 7 EXPCON_IO32
"D6", # 8 EXPCON_IO33
"E7", # 9 EXPCON_IO34
"D7", # 10 EXPCON_IO35
"B11", # 11 EXPCON_IO36
"B6", # 12 EXPCON_IO37
"E9", # 13 EXPCON_IO38
"D9", # 14 EXPCON_IO39
"B8", # 15 EXPCON_IO40
"C8", # 16 EXPCON_IO41
"D8", # 17 EXPCON_IO42
"E8", # 18 EXPCON_IO43
"C7", # 19 EXPCON_IO44
"C6", # 20 EXPCON_IO45
"None", # 21 +5V
"None", # 22 GND
"None", # 23 +2V5
"None", # 24 GND
"None", # 25 +3V3
"None", # 26 GND
"None", # 27 +3V3
"None", # 28 GND
"None", # 29 EXPCON_OSC
"None", # 30 GND
"None", # 31 EXPCON_CLKIN
"None", # 32 GND
"None", # 33 EXPCON_CLKOUT
"None", # 34 GND
"None", # 35 +3V3
"None", # 36 GND
"None", # 37 +3V3
"None", # 38 GND
"None", # 39 +3V3
"None", # 40 GND
),
]
class Platform(LatticePlatform): class Platform(LatticePlatform):
default_clk_name = "clk100" default_clk_name = "clk100"
default_clk_period = 10 default_clk_period = 10
def __init__(self, **kwargs): def __init__(self, **kwargs):
LatticePlatform.__init__(self, "LFE5UM5G-45F-8BG381C", _io, **kwargs) LatticePlatform.__init__(self, "LFE5UM5G-45F-8BG381C", _io, _connectors, **kwargs)
def do_finalize(self, fragment): def do_finalize(self, fragment):
LatticePlatform.do_finalize(self, fragment) LatticePlatform.do_finalize(self, fragment)
......
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment