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Kestrel Collaboration
Kestrel LiteX
migen
Commits
aea08419
Commit
aea08419
authored
5 years ago
by
Sebastien Bourdeauducq
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metlino: add gth_clk200 and port0
parent
7299f4eb
Changes
1
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1 changed file
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12 additions
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1 deletion
+12
-1
migen/build/platforms/sinara/metlino.py
migen/build/platforms/sinara/metlino.py
+12
-1
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migen/build/platforms/sinara/metlino.py
View file @
aea08419
...
@@ -60,7 +60,18 @@ _io = [
...
@@ -60,7 +60,18 @@ _io = [
Subsignal
(
"reset_n"
,
Pins
(
"AJ14"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"reset_n"
,
Pins
(
"AJ14"
),
IOStandard
(
"SSTL15"
)),
Misc
(
"SLEW=FAST"
),
Misc
(
"SLEW=FAST"
),
Misc
(
"OUTPUT_IMPEDANCE=RDRV_40_40"
)
Misc
(
"OUTPUT_IMPEDANCE=RDRV_40_40"
)
)
),
(
"gth_clk200"
,
0
,
Subsignal
(
"p"
,
Pins
(
"Y6"
)),
Subsignal
(
"n"
,
Pins
(
"Y5"
))
),
(
"port0"
,
0
,
Subsignal
(
"txp"
,
Pins
(
"B6"
)),
Subsignal
(
"txn"
,
Pins
(
"B5"
)),
Subsignal
(
"rxp"
,
Pins
(
"A4"
)),
Subsignal
(
"rxn"
,
Pins
(
"A3"
))
),
]
]
...
...
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