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Kestrel Collaboration
Kestrel LiteX
migen
Commits
7299f4eb
Commit
7299f4eb
authored
5 years ago
by
Sebastien Bourdeauducq
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metlino: add spiflash
parent
68156916
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migen/build/platforms/sinara/metlino.py
migen/build/platforms/sinara/metlino.py
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migen/build/platforms/sinara/metlino.py
View file @
7299f4eb
...
@@ -11,6 +11,15 @@ _io = [
...
@@ -11,6 +11,15 @@ _io = [
IOStandard
(
"LVCMOS33"
)
IOStandard
(
"LVCMOS33"
)
),
),
# this is the second SPI flash (not containing the bitstream)
# clock is shared with the bitstream flash and needs to be accessed
# through STARTUPE3
(
"spiflash"
,
0
,
Subsignal
(
"cs_n"
,
Pins
(
"G26"
)),
Subsignal
(
"dq"
,
Pins
(
"M20 L20 R21 R22"
)),
IOStandard
(
"LVCMOS33"
)
),
(
"ddram"
,
0
,
(
"ddram"
,
0
,
Subsignal
(
"a"
,
Pins
(
Subsignal
(
"a"
,
Pins
(
"AE17 AL17 AG16 AG17 AD16 AH14 AD15 AK15"
,
"AE17 AL17 AG16 AG17 AD16 AH14 AD15 AK15"
,
...
...
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