Commit a79badb1 authored by Robert Jordens's avatar Robert Jordens
Browse files

kasli: add internal VREF

parent 2e73dbdd
...@@ -173,3 +173,5 @@ class Platform(XilinxPlatform): ...@@ -173,3 +173,5 @@ class Platform(XilinxPlatform):
XilinxPlatform.__init__( XilinxPlatform.__init__(
self, "xc7a100t-fgg484-2", _io, _connectors, self, "xc7a100t-fgg484-2", _io, _connectors,
toolchain="vivado") toolchain="vivado")
self.add_platform_command(
"set_property INTERNAL_VREF 0.750 [get_iobanks 35]")
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