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Kestrel Collaboration
Kestrel LiteX
migen
Commits
a79badb1
Commit
a79badb1
authored
7 years ago
by
Robert Jordens
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kasli: add internal VREF
parent
2e73dbdd
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migen/build/platforms/sinara/kasli.py
migen/build/platforms/sinara/kasli.py
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migen/build/platforms/sinara/kasli.py
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a79badb1
...
@@ -173,3 +173,5 @@ class Platform(XilinxPlatform):
...
@@ -173,3 +173,5 @@ class Platform(XilinxPlatform):
XilinxPlatform
.
__init__
(
XilinxPlatform
.
__init__
(
self
,
"xc7a100t-fgg484-2"
,
_io
,
_connectors
,
self
,
"xc7a100t-fgg484-2"
,
_io
,
_connectors
,
toolchain
=
"vivado"
)
toolchain
=
"vivado"
)
self
.
add_platform_command
(
"set_property INTERNAL_VREF 0.750 [get_iobanks 35]"
)
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