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Kestrel Collaboration
Kestrel LiteX
migen
Commits
a728e6a1
Commit
a728e6a1
authored
7 years ago
by
William D. Jones
Committed by
Sébastien Bourdeauducq
7 years ago
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build/platforms: Add tinyfpga_b platform and programmer.
parent
109f2dd1
Changes
2
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+50
-0
migen/build/lattice/programmer.py
migen/build/lattice/programmer.py
+10
-0
migen/build/platforms/tinyfpga_b.py
migen/build/platforms/tinyfpga_b.py
+40
-0
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migen/build/lattice/programmer.py
View file @
a728e6a1
...
@@ -37,3 +37,13 @@ class IceBurnProgrammer(GenericProgrammer):
...
@@ -37,3 +37,13 @@ class IceBurnProgrammer(GenericProgrammer):
def
load_bitstream
(
self
,
bitstream_file
):
def
load_bitstream
(
self
,
bitstream_file
):
subprocess
.
call
([
self
.
iceburn
,
"-evw"
,
bitstream_file
])
subprocess
.
call
([
self
.
iceburn
,
"-evw"
,
bitstream_file
])
class
TinyFpgaBProgrammer
(
GenericProgrammer
):
needs_bitreverse
=
False
# The default flash address you probably want is 0x30000; the image at
# address 0 is for the bootloader.
def
flash
(
self
,
address
,
bitstream_file
):
subprocess
.
call
([
"tinyfpgab"
,
"-a"
,
str
(
address
),
"-p"
,
bitstream_file
])
This diff is collapsed.
Click to expand it.
migen/build/platforms/tinyfpga_b.py
0 → 100644
View file @
a728e6a1
from
migen.build.generic_platform
import
*
from
migen.build.lattice
import
LatticePlatform
from
migen.build.lattice.programmer
import
TinyFpgaBProgrammer
_io
=
[
(
"usb"
,
0
,
Subsignal
(
"d_p"
,
Pins
(
"A3"
)),
Subsignal
(
"d_n"
,
Pins
(
"A4"
)),
IOStandard
(
"LVCMOS33"
)
),
(
"spiflash"
,
0
,
Subsignal
(
"cs_n"
,
Pins
(
"F7"
),
IOStandard
(
"LVCMOS33"
)),
Subsignal
(
"clk"
,
Pins
(
"G7"
),
IOStandard
(
"LVCMOS33"
)),
Subsignal
(
"mosi"
,
Pins
(
"G6"
),
IOStandard
(
"LVCMOS33"
)),
Subsignal
(
"miso"
,
Pins
(
"H7"
),
IOStandard
(
"LVCMOS33"
))
),
(
"clk16"
,
0
,
Pins
(
"B4"
),
IOStandard
(
"LVCMOS33"
))
]
_connectors
=
[
# B2-J1, Pins 4-13
# D9-C9, Pins 18-19, Pins 21-24
# E8, Pin 20 (Input only)
(
"GPIO"
,
"B2 A2 A1 B1 C1 D1 E1 G1 H1 J1 D9 C9 A9 A8 A7 A6"
),
(
"GBIN"
,
"E8"
)
]
class
Platform
(
LatticePlatform
):
default_clk_name
=
"clk16"
default_clk_period
=
62.5
def
__init__
(
self
):
LatticePlatform
.
__init__
(
self
,
"ice40-lp8k-cm81"
,
_io
,
_connectors
,
toolchain
=
"icestorm"
)
def
create_programmer
(
self
):
return
TinyFpgaBProgrammer
()
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