Skip to content
GitLab
Projects
Groups
Snippets
Help
Loading...
Help
Help
Support
Community forum
Keyboard shortcuts
?
Submit feedback
Contribute to GitLab
Sign in / Register
Toggle navigation
Open sidebar
Kestrel Collaboration
Kestrel LiteX
migen
Commits
9fd7a48a
Commit
9fd7a48a
authored
5 years ago
by
Sebastien Bourdeauducq
Browse files
Options
Download
Email Patches
Plain Diff
remove Roach
parent
9d90900d
Changes
2
Hide whitespace changes
Inline
Side-by-side
Showing
2 changed files
with
0 additions
and
40 deletions
+0
-40
migen/build/platforms/roach.py
migen/build/platforms/roach.py
+0
-35
migen/test/test_platform.py
migen/test/test_platform.py
+0
-5
No files found.
migen/build/platforms/roach.py
deleted
100644 → 0
View file @
9d90900d
from
migen.build.generic_platform
import
*
from
migen.build.xilinx
import
XilinxPlatform
_io
=
[
(
"epb"
,
0
,
Subsignal
(
"cs_n"
,
Pins
(
"K13"
)),
Subsignal
(
"r_w_n"
,
Pins
(
"AF20"
)),
Subsignal
(
"be_n"
,
Pins
(
"AF14 AF18"
)),
Subsignal
(
"oe_n"
,
Pins
(
"AF21"
)),
Subsignal
(
"addr"
,
Pins
(
"AE23 AE22 AG18 AG12 AG15 AG23 AF19 AE12 AG16 AF13 AG20 AF23"
,
"AH17 AH15 L20 J22 H22 L15 L16 K22 K21 K16 J15"
)),
Subsignal
(
"addr_gp"
,
Pins
(
"L21 G22 K23 K14 L14 J12"
)),
Subsignal
(
"data"
,
Pins
(
"AF15 AE16 AE21 AD20 AF16 AE17 AE19 AD19 AG22 AH22 AH12 AG13"
,
"AH20 AH19 AH14 AH13"
)),
Subsignal
(
"rdy"
,
Pins
(
"K12"
)),
IOStandard
(
"LVCMOS33"
)
),
(
"roach_clocks"
,
0
,
Subsignal
(
"epb_clk"
,
Pins
(
"AH18"
),
IOStandard
(
"LVCMOS33"
)),
Subsignal
(
"sys_clk_n"
,
Pins
(
"H13"
)),
Subsignal
(
"sys_clk_p"
,
Pins
(
"J14"
)),
Subsignal
(
"aux0_clk_p"
,
Pins
(
"G15"
)),
Subsignal
(
"aux0_clk_n"
,
Pins
(
"G16"
)),
Subsignal
(
"aux1_clk_p"
,
Pins
(
"H14"
)),
Subsignal
(
"aux1_clk_n"
,
Pins
(
"H15"
)),
Subsignal
(
"dly_clk_n"
,
Pins
(
"J17"
)),
Subsignal
(
"dly_clk_p"
,
Pins
(
"J16"
)),
),
]
class
Platform
(
XilinxPlatform
):
def
__init__
(
self
):
XilinxPlatform
.
__init__
(
self
,
"xc5vsx95t-ff1136-1"
,
_io
)
This diff is collapsed.
Click to expand it.
migen/test/test_platform.py
View file @
9fd7a48a
...
@@ -57,11 +57,6 @@ class TestExamplesPlatform(unittest.TestCase):
...
@@ -57,11 +57,6 @@ class TestExamplesPlatform(unittest.TestCase):
def
test_platforms
(
self
):
def
test_platforms
(
self
):
for
mod
,
name
in
_find_platforms
(
migen
.
build
.
platforms
):
for
mod
,
name
in
_find_platforms
(
migen
.
build
.
platforms
):
with
self
.
subTest
(
mod
=
mod
,
name
=
name
):
with
self
.
subTest
(
mod
=
mod
,
name
=
name
):
# Roach has no default clock, so expect failure/skip.
if
name
==
"roach"
:
raise
unittest
.
SkipTest
(
"Roach has no default clock for test."
)
run_toolchain_var
=
"MIGEN_RUN_TOOLCHAIN_{}"
.
format
(
run_toolchain_var
=
"MIGEN_RUN_TOOLCHAIN_{}"
.
format
(
name
.
upper
())
name
.
upper
())
...
...
This diff is collapsed.
Click to expand it.
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
.
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment