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Kestrel Collaboration
Kestrel LiteX
migen
Commits
8b64f860
Commit
8b64f860
authored
8 years ago
by
Sebastien Bourdeauducq
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fhdl/verilog: call get_ports() to get default ios
parent
462005f1
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6 additions
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3 deletions
+6
-3
migen/fhdl/verilog.py
migen/fhdl/verilog.py
+6
-3
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migen/fhdl/verilog.py
View file @
8b64f860
...
...
@@ -274,11 +274,14 @@ def convert(f, ios=None, name="top",
create_clock_domains
=
True
,
display_run
=
False
,
asic_syntax
=
False
):
r
=
ConvOutput
()
if
not
isinstance
(
f
,
_Fragment
):
f
=
f
.
get_fragment
()
if
ios
is
None
:
ios
=
set
()
if
hasattr
(
f
,
"get_ports"
):
ios
=
f
.
get_ports
()
else
:
ios
=
set
()
ios
=
set
(
ios
)
if
not
isinstance
(
f
,
_Fragment
):
f
=
f
.
get_fragment
()
for
cd_name
in
sorted
(
list_clock_domains
(
f
)):
try
:
...
...
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