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Kestrel Collaboration
Kestrel LiteX
migen
Commits
8a61d9d1
Commit
8a61d9d1
authored
12 years ago
by
Sebastien Bourdeauducq
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bus/csr: Rename a->adr d->dat to be consistent with the other buses
parent
d6da88d1
Changes
3
Hide whitespace changes
Inline
Side-by-side
Showing
3 changed files
with
22 additions
and
22 deletions
+22
-22
migen/bank/csrgen.py
migen/bank/csrgen.py
+11
-11
migen/bus/csr.py
migen/bus/csr.py
+7
-7
migen/bus/wishbone2csr.py
migen/bus/wishbone2csr.py
+4
-4
No files found.
migen/bank/csrgen.py
View file @
8a61d9d1
...
...
@@ -13,7 +13,7 @@ class Bank:
sync
=
[]
sel
=
Signal
()
comb
.
append
(
sel
.
eq
(
self
.
interface
.
a_i
[
9
:]
==
Constant
(
self
.
address
,
BV
(
5
))))
comb
.
append
(
sel
.
eq
(
self
.
interface
.
a
dr
_i
[
9
:]
==
Constant
(
self
.
address
,
BV
(
5
))))
desc_exp
=
expand_description
(
self
.
description
,
8
)
nbits
=
bits_for
(
len
(
desc_exp
)
-
1
)
...
...
@@ -22,29 +22,29 @@ class Bank:
bwcases
=
[]
for
i
,
reg
in
enumerate
(
desc_exp
):
if
isinstance
(
reg
,
RegisterRaw
):
comb
.
append
(
reg
.
r
.
eq
(
self
.
interface
.
d_i
[:
reg
.
size
]))
comb
.
append
(
reg
.
r
.
eq
(
self
.
interface
.
d
at
_i
[:
reg
.
size
]))
comb
.
append
(
reg
.
re
.
eq
(
sel
&
\
self
.
interface
.
we_i
&
\
(
self
.
interface
.
a_i
[:
nbits
]
==
Constant
(
i
,
BV
(
nbits
)))))
(
self
.
interface
.
a
dr
_i
[:
nbits
]
==
Constant
(
i
,
BV
(
nbits
)))))
elif
isinstance
(
reg
,
RegisterFields
):
bwra
=
[
Constant
(
i
,
BV
(
nbits
))]
offset
=
0
for
field
in
reg
.
fields
:
if
field
.
access_bus
==
WRITE_ONLY
or
field
.
access_bus
==
READ_WRITE
:
bwra
.
append
(
field
.
storage
.
eq
(
self
.
interface
.
d_i
[
offset
:
offset
+
field
.
size
]))
bwra
.
append
(
field
.
storage
.
eq
(
self
.
interface
.
d
at
_i
[
offset
:
offset
+
field
.
size
]))
offset
+=
field
.
size
if
len
(
bwra
)
>
1
:
bwcases
.
append
(
bwra
)
else
:
raise
TypeError
if
bwcases
:
sync
.
append
(
If
(
sel
&
self
.
interface
.
we_i
,
Case
(
self
.
interface
.
a_i
[:
nbits
],
*
bwcases
)))
sync
.
append
(
If
(
sel
&
self
.
interface
.
we_i
,
Case
(
self
.
interface
.
a
dr
_i
[:
nbits
],
*
bwcases
)))
# Bus reads
brcases
=
[]
for
i
,
reg
in
enumerate
(
desc_exp
):
if
isinstance
(
reg
,
RegisterRaw
):
brcases
.
append
([
Constant
(
i
,
BV
(
nbits
)),
self
.
interface
.
d_o
.
eq
(
reg
.
w
)])
brcases
.
append
([
Constant
(
i
,
BV
(
nbits
)),
self
.
interface
.
d
at
_o
.
eq
(
reg
.
w
)])
elif
isinstance
(
reg
,
RegisterFields
):
brs
=
[]
reg_readable
=
False
...
...
@@ -56,16 +56,16 @@ class Bank:
brs
.
append
(
Constant
(
0
,
BV
(
field
.
size
)))
if
reg_readable
:
if
len
(
brs
)
>
1
:
brcases
.
append
([
Constant
(
i
,
BV
(
nbits
)),
self
.
interface
.
d_o
.
eq
(
Cat
(
*
brs
))])
brcases
.
append
([
Constant
(
i
,
BV
(
nbits
)),
self
.
interface
.
d
at
_o
.
eq
(
Cat
(
*
brs
))])
else
:
brcases
.
append
([
Constant
(
i
,
BV
(
nbits
)),
self
.
interface
.
d_o
.
eq
(
brs
[
0
])])
brcases
.
append
([
Constant
(
i
,
BV
(
nbits
)),
self
.
interface
.
d
at
_o
.
eq
(
brs
[
0
])])
else
:
raise
TypeError
if
brcases
:
sync
.
append
(
self
.
interface
.
d_o
.
eq
(
Constant
(
0
,
BV
(
8
))))
sync
.
append
(
If
(
sel
,
Case
(
self
.
interface
.
a_i
[:
nbits
],
*
brcases
)))
sync
.
append
(
self
.
interface
.
d
at
_o
.
eq
(
Constant
(
0
,
BV
(
8
))))
sync
.
append
(
If
(
sel
,
Case
(
self
.
interface
.
a
dr
_i
[:
nbits
],
*
brcases
)))
else
:
comb
.
append
(
self
.
interface
.
d_o
.
eq
(
Constant
(
0
,
BV
(
8
))))
comb
.
append
(
self
.
interface
.
d
at
_o
.
eq
(
Constant
(
0
,
BV
(
8
))))
# Device access
for
reg
in
self
.
description
:
...
...
This diff is collapsed.
Click to expand it.
migen/bus/csr.py
View file @
8a61d9d1
...
...
@@ -3,10 +3,10 @@ from migen.corelogic.misc import optree
from
migen.bus.simple
import
Simple
_desc
=
[
(
True
,
"a"
,
14
),
(
True
,
"a
dr
"
,
14
),
(
True
,
"we"
,
1
),
(
True
,
"d"
,
8
),
(
False
,
"d"
,
8
)
(
True
,
"d
at
"
,
8
),
(
False
,
"d
at
"
,
8
)
]
class
Master
(
Simple
):
...
...
@@ -25,9 +25,9 @@ class Interconnect:
def
get_fragment
(
self
):
comb
=
[]
for
slave
in
self
.
slaves
:
comb
.
append
(
slave
.
a_i
.
eq
(
self
.
master
.
a_o
))
comb
.
append
(
slave
.
a
dr
_i
.
eq
(
self
.
master
.
a
dr
_o
))
comb
.
append
(
slave
.
we_i
.
eq
(
self
.
master
.
we_o
))
comb
.
append
(
slave
.
d_i
.
eq
(
self
.
master
.
d_o
))
rb
=
optree
(
'|'
,
[
slave
.
d_o
for
slave
in
self
.
slaves
])
comb
.
append
(
self
.
master
.
d_i
.
eq
(
rb
))
comb
.
append
(
slave
.
d
at
_i
.
eq
(
self
.
master
.
d
at
_o
))
rb
=
optree
(
"|"
,
[
slave
.
d
at
_o
for
slave
in
self
.
slaves
])
comb
.
append
(
self
.
master
.
d
at
_i
.
eq
(
rb
))
return
Fragment
(
comb
)
This diff is collapsed.
Click to expand it.
migen/bus/wishbone2csr.py
View file @
8a61d9d1
...
...
@@ -3,7 +3,7 @@ from migen.bus import csr
from
migen.fhdl.structure
import
*
from
migen.corelogic
import
timeline
class
WB2CSR
()
:
class
WB2CSR
:
def
__init__
(
self
):
self
.
wishbone
=
wishbone
.
Slave
()
self
.
csr
=
csr
.
Master
()
...
...
@@ -15,8 +15,8 @@ class WB2CSR():
def
get_fragment
(
self
):
sync
=
[
self
.
csr
.
we_o
.
eq
(
0
),
self
.
csr
.
d_o
.
eq
(
self
.
wishbone
.
dat_i
[:
8
]),
self
.
csr
.
a_o
.
eq
(
self
.
wishbone
.
adr_i
[:
14
]),
self
.
wishbone
.
dat_o
.
eq
(
self
.
csr
.
d_i
)
self
.
csr
.
d
at
_o
.
eq
(
self
.
wishbone
.
dat_i
[:
8
]),
self
.
csr
.
a
dr
_o
.
eq
(
self
.
wishbone
.
adr_i
[:
14
]),
self
.
wishbone
.
dat_o
.
eq
(
self
.
csr
.
d
at
_i
)
]
return
Fragment
(
sync
=
sync
)
+
self
.
timeline
.
get_fragment
()
This diff is collapsed.
Click to expand it.
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