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Kestrel Collaboration
Kestrel LiteX
migen
Commits
8a1081ed
Commit
8a1081ed
authored
8 years ago
by
Ben Reynwar
Committed by
Sébastien Bourdeauducq
8 years ago
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Set the width and signedness of the reset value.
parent
e8803c99
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migen/fhdl/structure.py
migen/fhdl/structure.py
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migen/fhdl/structure.py
View file @
8a1081ed
...
@@ -334,6 +334,8 @@ class Signal(_Value):
...
@@ -334,6 +334,8 @@ class Signal(_Value):
self
.
nbits
,
self
.
signed
=
bits_sign
self
.
nbits
,
self
.
signed
=
bits_sign
else
:
else
:
self
.
nbits
,
self
.
signed
=
bits_sign
,
False
self
.
nbits
,
self
.
signed
=
bits_sign
,
False
if
isinstance
(
reset
,
(
bool
,
int
)):
reset
=
Constant
(
reset
,
(
self
.
nbits
,
self
.
signed
))
if
not
isinstance
(
self
.
nbits
,
int
)
or
self
.
nbits
<=
0
:
if
not
isinstance
(
self
.
nbits
,
int
)
or
self
.
nbits
<=
0
:
raise
ValueError
(
"Signal width must be a strictly positive integer"
)
raise
ValueError
(
"Signal width must be a strictly positive integer"
)
if
attr
is
None
:
if
attr
is
None
:
...
...
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