Commit 5bc22e71 authored by Paweł Kulik's avatar Paweł Kulik Committed by Sébastien Bourdeauducq
Browse files

Added most of Basemod AFE pins for Sayma AMC and RTM

Signed-off-by: default avatarPaweł Kulik <pawel.kulik@creotech.pl>
parent 6c8c6aab
......@@ -341,6 +341,73 @@ _io = [
Subsignal("n", Pins("F17")),
IOStandard("DIFF_SSTL15_DCI")
),
("basemod0_adc_spi_p", 0,
Subsignal("clk", Pins("D8")),
Subsignal("miso", Pins("L8"), Misc("DIFF_TERM_ADV=TERM_100")),
IOStandard("LVDS")
),
("basemod0_adc_spi_n", 0,
Subsignal("clk", Pins("C8")),
Subsignal("miso", Pins("K8"), Misc("DIFF_TERM_ADV=TERM_100")),
IOStandard("LVDS")
),
("basemod0_adc_cnv", 0,
Subsignal("p", Pins("B9")),
Subsignal("n", Pins("A9")),
IOStandard("LVDS"), Misc("DIFF_TERM_ADV=TERM_100"),
),
("basemod0_adc_sdr", 0, Pins("D13"), IOStandard("LVCMOS18")),
("basemod0_adc_data_p", 0,
Subsignal("clkout", Pins("G10")),
Subsignal("sdoa", Pins("L8")),
Subsignal("sdob", Pins("C12")),
Subsignal("sdoc", Pins("A13")),
Subsignal("sdod", Pins("C11")),
IOStandard("LVDS"), Misc("DIFF_TERM_ADV=TERM_100")
),
("basemod0_adc_data_n", 0,
Subsignal("clkout", Pins("F10")),
Subsignal("sdoa", Pins("K8")),
Subsignal("sdob", Pins("B12")),
Subsignal("sdoc", Pins("A12")),
Subsignal("sdod", Pins("B11")),
IOStandard("LVDS"), Misc("DIFF_TERM_ADV=TERM_100")
),
("basemod0_led", 0, Pins("AB27"), IOStandard("LVCMOS18")),
("basemod0_led", 1, Pins("AA27"), IOStandard("LVCMOS18")),
("basemod0_led", 2, Pins("AF30"), IOStandard("LVCMOS18")),
("basemod0_led", 3, Pins("AG30"), IOStandard("LVCMOS18")),
("basemod0_led", 4, Pins("E13"), IOStandard("LVCMOS18")),
("basemod0_led", 5, Pins("F13"), IOStandard("LVCMOS18")),
("basemod0_led", 6, Pins("J11"), IOStandard("LVCMOS18")),
("basemod0_led", 7, Pins("K11"), IOStandard("LVCMOS18")),
("basemod1_adc_spi_p", 0,
Subsignal("clk", Pins("G9")),
Subsignal("miso", Pins("J9"), Misc("DIFF_TERM_ADV=TERM_100")),
IOStandard("LVDS")
),
("basemod1_adc_spi_n", 0,
Subsignal("clk", Pins("F9")),
Subsignal("miso", Pins("H9"), Misc("DIFF_TERM_ADV=TERM_100")),
IOStandard("LVDS")
),
("basemod1_adc_cnv", 0,
Subsignal("p", Pins("L13")),
Subsignal("n", Pins("K13")),
IOStandard("LVDS"), Misc("DIFF_TERM_ADV=TERM_100"),
),
("basemod1_adc_sdr", 0, Pins("AE28"), IOStandard("LVCMOS18")),
("basemod1_led", 0, Pins("AC27"), IOStandard("LVCMOS18")),
("basemod1_led", 1, Pins("AC26"), IOStandard("LVCMOS18")),
("basemod1_led", 2, Pins("AC24"), IOStandard("LVCMOS18")),
("basemod1_led", 3, Pins("AB24"), IOStandard("LVCMOS18")),
("basemod1_led", 4, Pins("Y27"), IOStandard("LVCMOS18")),
("basemod1_led", 5, Pins("Y26"), IOStandard("LVCMOS18")),
("basemod1_led", 6, Pins("C9"), IOStandard("LVCMOS18")),
("basemod1_led", 7, Pins("D9"), IOStandard("LVCMOS18")),
]
# differences with Sayma v1: CLK1_M2C, DP0_C2M, DP0_M2C, GBTCLK0_M2C, LA08
......
......@@ -118,9 +118,49 @@ _io = [
Subsignal("rxn", Pins("G3"))
),
# Bogus AFE pins for testing (TODO)
("allaki0_rfsw0", 0, Pins("E18"), IOStandard("LVCMOS25")),
("allaki0_rfsw1", 0, Pins("F17"), IOStandard("LVCMOS25")),
# AFE pins (WIP)
("basemod0_rfsw", 0, Pins("U16"), IOStandard("LVCMOS33")),
("basemod0_rfsw", 1, Pins("U14"), IOStandard("LVCMOS33")),
("basemod0_rfsw", 2, Pins("V14"), IOStandard("LVCMOS33")),
("basemod0_rfsw", 3, Pins("V12"), IOStandard("LVCMOS33")),
#AFE0 ADC amp
("basemod0_adc_amp_a0", 0, Pins("H16"), IOStandard("LVCMOS25")),
("basemod0_adc_amp_a0", 1, Pins("C17"), IOStandard("LVCMOS25")),
("basemod0_adc_amp_a0", 2, Pins("E17"), IOStandard("LVCMOS25")),
("basemod0_adc_amp_a0", 3, Pins("G14"), IOStandard("LVCMOS25")),
("basemod0_adc_amp_a1", 0, Pins("G16"), IOStandard("LVCMOS25")),
("basemod0_adc_amp_a1", 1, Pins("C18"), IOStandard("LVCMOS25")),
("basemod0_adc_amp_a1", 2, Pins("D18"), IOStandard("LVCMOS25")),
("basemod0_adc_amp_a1", 3, Pins("F14"), IOStandard("LVCMOS25")),
# AFE1 pins (WIP)
("basemod1_rfsw", 0, Pins("J16"), IOStandard("LVCMOS33")),
("basemod1_rfsw", 1, Pins("K15"), IOStandard("LVCMOS33")),
("basemod1_rfsw", 2, Pins("L15"), IOStandard("LVCMOS33")),
("basemod1_rfsw", 3, Pins("M15"), IOStandard("LVCMOS33")),
# AFE1 ADC amp
("basemod1_adc_amp_a0", 0, Pins("C11"), IOStandard("LVCMOS25")),
("basemod1_adc_amp_a0", 1, Pins("B9"), IOStandard("LVCMOS25")),
("basemod1_adc_amp_a0", 2, Pins("D9"), IOStandard("LVCMOS25")),
("basemod1_adc_amp_a0", 3, Pins("D8"), IOStandard("LVCMOS25")),
("basemod1_adc_amp_a1", 0, Pins("B11"), IOStandard("LVCMOS25")),
("basemod1_adc_amp_a1", 1, Pins("A9"), IOStandard("LVCMOS25")),
("basemod1_adc_amp_a1", 2, Pins("C9"), IOStandard("LVCMOS25")),
("basemod1_adc_amp_a1", 3, Pins("C8"), IOStandard("LVCMOS25")),
#Header I/O
("header_gpio", 0, Pins("B17"), IOStandard("LVCMOS25")),
("header_gpio", 1, Pins("C16"), IOStandard("LVCMOS25")),
("header_gpio", 2, Pins("A17"), IOStandard("LVCMOS25")),
("header_gpio", 3, Pins("B16"), IOStandard("LVCMOS25")),
("header_gpio", 4, Pins("D16"), IOStandard("LVCMOS25")),
("header_gpio", 5, Pins("E16"), IOStandard("LVCMOS25")),
("header_gpio", 6, Pins("A15"), IOStandard("LVCMOS25")),
("header_gpio", 7, Pins("B14"), IOStandard("LVCMOS25")),
("header_gpio", 8, Pins("C13"), IOStandard("LVCMOS25")),
("header_gpio", 9, Pins("D13"), IOStandard("LVCMOS25")),
]
class Platform(XilinxPlatform):
......
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