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Kestrel Collaboration
Kestrel LiteX
migen
Commits
587d2710
Commit
587d2710
authored
6 years ago
by
Adam Greig
Committed by
Sébastien Bourdeauducq
6 years ago
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fhdl/verilog: Don't emit constants larger than bit width for signed constants
parent
f5da0f76
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1
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+2
-2
migen/fhdl/verilog.py
migen/fhdl/verilog.py
+2
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migen/fhdl/verilog.py
View file @
587d2710
...
@@ -44,8 +44,8 @@ def _printsig(ns, s):
...
@@ -44,8 +44,8 @@ def _printsig(ns, s):
def
_printconstant
(
node
):
def
_printconstant
(
node
):
if
node
.
signed
:
if
node
.
signed
:
return
(
str
(
node
.
nbits
)
+
"'sd"
+
str
(
2
**
node
.
nbits
+
node
.
value
),
val
=
node
.
value
if
node
.
value
>=
0
else
2
**
node
.
nbits
+
node
.
value
True
)
return
(
str
(
node
.
nbits
)
+
"'sd"
+
str
(
val
),
True
)
else
:
else
:
return
str
(
node
.
nbits
)
+
"'d"
+
str
(
node
.
value
),
False
return
str
(
node
.
nbits
)
+
"'d"
+
str
(
node
.
value
),
False
...
...
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