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Kestrel Collaboration
Kestrel LiteX
migen
Commits
58126e08
Commit
58126e08
authored
8 years ago
by
Robert Jordens
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verilog: stable attr ordering
parent
6ffffd67
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migen/fhdl/verilog.py
migen/fhdl/verilog.py
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migen/fhdl/verilog.py
View file @
58126e08
...
@@ -168,7 +168,7 @@ def _list_comb_wires(f):
...
@@ -168,7 +168,7 @@ def _list_comb_wires(f):
def
_printattr
(
sig
,
attr_translate
):
def
_printattr
(
sig
,
attr_translate
):
r
=
""
r
=
""
firsta
=
True
firsta
=
True
for
attr
in
sig
.
attr
:
for
attr
in
sorted
(
sig
.
attr
)
:
if
isinstance
(
attr
,
tuple
):
if
isinstance
(
attr
,
tuple
):
# platform-dependent attribute
# platform-dependent attribute
attr_name
,
attr_value
=
attr
attr_name
,
attr_value
=
attr
...
...
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