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Kestrel Collaboration
Kestrel LiteX
migen
Commits
56e1b4ec
Commit
56e1b4ec
authored
4 years ago
by
Sebastien Bourdeauducq
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metlino: add DCXO control signals
parent
084e2a21
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migen/build/platforms/sinara/metlino.py
migen/build/platforms/sinara/metlino.py
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migen/build/platforms/sinara/metlino.py
View file @
56e1b4ec
...
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@@ -184,6 +184,17 @@ _io = [
Subsignal
(
"rxp"
,
Pins
(
"P2"
)),
Subsignal
(
"rxn"
,
Pins
(
"P1"
))
),
(
"ddmtd_main_dcxo_oe"
,
0
,
Pins
(
"AM11"
),
IOStandard
(
"LVCMOS33"
)),
(
"ddmtd_main_dcxo_i2c"
,
0
,
Subsignal
(
"scl"
,
Pins
(
"AN11"
)),
Subsignal
(
"sda"
,
Pins
(
"AN13"
)),
IOStandard
(
"LVCMOS33"
)),
(
"ddmtd_helper_dcxo_oe"
,
0
,
Pins
(
"AK12"
),
IOStandard
(
"LVCMOS33"
)),
(
"ddmtd_helper_dcxo_i2c"
,
0
,
Subsignal
(
"scl"
,
Pins
(
"AL12"
)),
Subsignal
(
"sda"
,
Pins
(
"AM12"
)),
IOStandard
(
"LVCMOS33"
)),
]
...
...
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