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Kestrel Collaboration
Kestrel LiteX
migen
Commits
40890b71
Commit
40890b71
authored
7 years ago
by
Robert Jordens
Browse files
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kasli: v1.0 pinout from schematics
parent
891562a6
Changes
1
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1 changed file
with
71 additions
and
56 deletions
+71
-56
migen/build/platforms/sinara/kasli.py
migen/build/platforms/sinara/kasli.py
+71
-56
No files found.
migen/build/platforms/sinara/kasli.py
View file @
40890b71
...
...
@@ -3,13 +3,13 @@ from migen.build.xilinx import XilinxPlatform
_io
=
[
(
"user_led"
,
0
,
Pins
(
"
Y19
"
),
IOStandard
(
"LVCMOS25"
)),
# LED_USER1
(
"user_led"
,
0
,
Pins
(
"
T16
"
),
IOStandard
(
"LVCMOS25"
)),
# LED_USER1
(
"clk50"
,
0
,
Pins
(
"
Y18
"
),
IOStandard
(
"LVCMOS25"
)),
(
"clk50"
,
0
,
Pins
(
"
W19
"
),
IOStandard
(
"LVCMOS25"
)),
(
"clk_fpgaio"
,
0
,
Subsignal
(
"p"
,
Pins
(
"
W19
"
)),
Subsignal
(
"n"
,
Pins
(
"
W20
"
)),
Subsignal
(
"p"
,
Pins
(
"
Y18
"
)),
Subsignal
(
"n"
,
Pins
(
"
Y19
"
)),
IOStandard
(
"LVDS25"
),
),
...
...
@@ -20,22 +20,25 @@ _io = [
),
(
"serial"
,
0
,
Subsignal
(
"tx"
,
Pins
(
"
V22
"
)),
Subsignal
(
"rx"
,
Pins
(
"
P16
"
)),
Subsignal
(
"tx"
,
Pins
(
"
N13
"
)),
Subsignal
(
"rx"
,
Pins
(
"
N17
"
)),
IOStandard
(
"LVCMOS25"
)
),
(
"clk_sel"
,
0
,
Pins
(
"W22"
),
IOStandard
(
"LVCMOS25"
)),
(
"clk_sel"
,
0
,
Pins
(
"F21"
),
IOStandard
(
"LVCMOS25"
)),
(
"vusb_present"
,
0
,
Pins
(
"M17"
),
IOStandard
(
"LVCMOS25"
)),
(
"i2c"
,
0
,
Subsignal
(
"scl"
,
Pins
(
"
U21
"
)),
Subsignal
(
"sda"
,
Pins
(
"
T21
"
)),
Subsignal
(
"scl"
,
Pins
(
"
J16
"
)),
Subsignal
(
"sda"
,
Pins
(
"
F15
"
)),
IOStandard
(
"LVCMOS25"
)
),
(
"spiflash"
,
0
,
Subsignal
(
"cs_n"
,
Pins
(
"T19"
)),
Subsignal
(
"dq"
,
Pins
(
"P22 R22 P21 R21"
)),
# "clk" is on CCLK
IOStandard
(
"LVCMOS25"
)
),
...
...
@@ -44,10 +47,10 @@ _io = [
Subsignal
(
"n"
,
Pins
(
"E6"
)),
),
#
("clk125_gtp", 0,
#
Subsignal("p", Pins("F10")),
#
Subsignal("n", Pins("E10")),
#
),
(
"clk125_gtp"
,
0
,
Subsignal
(
"p"
,
Pins
(
"F10"
)),
Subsignal
(
"n"
,
Pins
(
"E10"
)),
),
(
"sfp_gtp"
,
0
,
Subsignal
(
"txp"
,
Pins
(
"B4"
)),
...
...
@@ -56,14 +59,14 @@ _io = [
Subsignal
(
"rxn"
,
Pins
(
"A8"
)),
),
(
"sfp"
,
0
,
Subsignal
(
"mod_def1"
,
Pins
(
"
T3
"
)),
Subsignal
(
"mod_def2"
,
Pins
(
"
U7
"
)),
Subsignal
(
"los"
,
Pins
(
"
U17
"
)),
Subsignal
(
"mod_present"
,
Pins
(
"U1
8
"
)),
Subsignal
(
"rate_select"
,
Pins
(
"
P14
"
)),
Subsignal
(
"mod_def1"
,
Pins
(
"
U7
"
)),
Subsignal
(
"mod_def2"
,
Pins
(
"
T3
"
)),
Subsignal
(
"los"
,
Pins
(
"
P15
"
)),
Subsignal
(
"mod_present"
,
Pins
(
"U1
6
"
)),
Subsignal
(
"rate_select"
,
Pins
(
"
N15
"
)),
Subsignal
(
"tx_disable"
,
Pins
(
"R14"
)),
Subsignal
(
"tx_fault"
,
Pins
(
"
R18
"
)),
Subsignal
(
"led"
,
Pins
(
"
N17
"
)),
Subsignal
(
"tx_fault"
,
Pins
(
"
N14
"
)),
Subsignal
(
"led"
,
Pins
(
"
P16
"
)),
IOStandard
(
"LVCMOS25"
)
),
...
...
@@ -74,8 +77,14 @@ _io = [
Subsignal
(
"rxn"
,
Pins
(
"C11"
)),
),
(
"sfp"
,
1
,
# ...
Subsignal
(
"led"
,
Pins
(
"T18"
)),
Subsignal
(
"mod_def1"
,
Pins
(
"P17"
)),
Subsignal
(
"mod_def2"
,
Pins
(
"U18"
)),
Subsignal
(
"los"
,
Pins
(
"R18"
)),
Subsignal
(
"mod_present"
,
Pins
(
"W20"
)),
Subsignal
(
"rate_select"
,
Pins
(
"T18"
)),
Subsignal
(
"tx_disable"
,
Pins
(
"R17"
)),
Subsignal
(
"tx_fault"
,
Pins
(
"U17"
)),
Subsignal
(
"led"
,
Pins
(
"R19"
)),
IOStandard
(
"LVCMOS25"
)
),
...
...
@@ -86,8 +95,14 @@ _io = [
Subsignal
(
"rxn"
,
Pins
(
"A10"
)),
),
(
"sfp"
,
2
,
# ...
Subsignal
(
"led"
,
Pins
(
"P20"
)),
Subsignal
(
"mod_def1"
,
Pins
(
"P14"
)),
Subsignal
(
"mod_def2"
,
Pins
(
"P20"
)),
Subsignal
(
"los"
,
Pins
(
"V22"
)),
Subsignal
(
"mod_present"
,
Pins
(
"T21"
)),
Subsignal
(
"rate_select"
,
Pins
(
"T20"
)),
Subsignal
(
"tx_disable"
,
Pins
(
"U21"
)),
Subsignal
(
"tx_fault"
,
Pins
(
"R16"
)),
Subsignal
(
"led"
,
Pins
(
"P19"
)),
IOStandard
(
"LVCMOS25"
)
),
...
...
@@ -100,27 +115,27 @@ _io = [
(
"ddram"
,
0
,
Subsignal
(
"a"
,
Pins
(
"
K2 G2 F3 J5 E2 H5 J2 K1
"
"
D1 E
1
D
2
A1 C2 B1 F4
"
),
"
L6 M5 P6 K6 M1 M3 N2 N7
"
"
P
1
P
2
L4 N5 L3 R1 N3
"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"ba"
,
Pins
(
"
H2 J1 G1
"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"ras_n"
,
Pins
(
"
K
4"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"cas_n"
,
Pins
(
"
G4
"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"we_n"
,
Pins
(
"
F1
"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"ba"
,
Pins
(
"
L5 M2 N4
"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"ras_n"
,
Pins
(
"
J
4"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"cas_n"
,
Pins
(
"
J6
"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"we_n"
,
Pins
(
"
K3
"
),
IOStandard
(
"SSTL15"
)),
# Subsignal("cs_n", Pins(""), IOStandard("SSTL15")),
Subsignal
(
"dm"
,
Pins
(
"
J4 N4
"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"dm"
,
Pins
(
"
G2 E2
"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"dq"
,
Pins
(
"
L
4
L
5
J6 K6 K3 L3 M2 M3
"
"
P
1
R
1
N2 P2 M5 M6 N5 P6
"
),
"
G3 J1 H
4
H
5
H2 K1 H3 J5
"
"
G
1
B
1
F1 F3 C2 A1 D2 B2
"
),
IOStandard
(
"SSTL15"
),
Misc
(
"IN_TERM=UNTUNED_SPLIT_50"
)),
Subsignal
(
"dqs_p"
,
Pins
(
"
M1 P5
"
),
IOStandard
(
"DIFF_SSTL15"
)),
Subsignal
(
"dqs_n"
,
Pins
(
"
L1 P4
"
),
IOStandard
(
"DIFF_SSTL15"
)),
Subsignal
(
"clk_p"
,
Pins
(
"
H3
"
),
IOStandard
(
"DIFF_SSTL15"
)),
Subsignal
(
"clk_n"
,
Pins
(
"
G3
"
),
IOStandard
(
"DIFF_SSTL15"
)),
Subsignal
(
"cke"
,
Pins
(
"
B2
"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"odt"
,
Pins
(
"
H
4"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"reset_n"
,
Pins
(
"
L6
"
),
IOStandard
(
"LVCMOS15"
)),
Subsignal
(
"dqs_p"
,
Pins
(
"
K2 E1
"
),
IOStandard
(
"DIFF_SSTL15"
)),
Subsignal
(
"dqs_n"
,
Pins
(
"
J2 D1
"
),
IOStandard
(
"DIFF_SSTL15"
)),
Subsignal
(
"clk_p"
,
Pins
(
"
P5
"
),
IOStandard
(
"DIFF_SSTL15"
)),
Subsignal
(
"clk_n"
,
Pins
(
"
P4
"
),
IOStandard
(
"DIFF_SSTL15"
)),
Subsignal
(
"cke"
,
Pins
(
"
L1
"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"odt"
,
Pins
(
"
K
4"
),
IOStandard
(
"SSTL15"
)),
Subsignal
(
"reset_n"
,
Pins
(
"
G4
"
),
IOStandard
(
"LVCMOS15"
)),
Misc
(
"SLEW=FAST"
),
),
]
...
...
@@ -128,22 +143,22 @@ _io = [
_connectors
=
[
(
"EEM0"
,
{
"D0_CC_P"
:
"
V
4"
,
"D0_CC_N"
:
"
W
4"
,
"D1_P"
:
"
T1
"
,
"D1_N"
:
"
U1
"
,
"D2_P"
:
"
U2
"
,
"D2_N"
:
"
V2
"
,
"D3_P"
:
"
R3
"
,
"D3_N"
:
"
R
2"
,
"D4_P"
:
"W
2
"
,
"D4_N"
:
"Y
2
"
,
"D5_P"
:
"W
1
"
,
"D6_P"
:
"Y
1
"
,
"D6_N"
:
"
U3
"
,
"D5_N"
:
"
V3
"
,
"D7_P"
:
"
AA1
"
,
"D7_N"
:
"A
B1
"
,
"D0_CC_P"
:
"
R
4"
,
"D0_CC_N"
:
"
T
4"
,
"D1_P"
:
"
R3
"
,
"D1_N"
:
"
R2
"
,
"D2_P"
:
"
T1
"
,
"D2_N"
:
"
U1
"
,
"D3_P"
:
"
U2
"
,
"D3_N"
:
"
V
2"
,
"D4_P"
:
"W
1
"
,
"D4_N"
:
"Y
1
"
,
"D5_P"
:
"W
2
"
,
"D6_P"
:
"Y
2
"
,
"D6_N"
:
"
AA1
"
,
"D5_N"
:
"
AB1
"
,
"D7_P"
:
"
Y4
"
,
"D7_N"
:
"A
A4
"
,
}),
# ...
...
...
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