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Kestrel Collaboration
Kestrel LiteX
migen
Commits
383512b4
Commit
383512b4
authored
5 years ago
by
Sebastien Bourdeauducq
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sayma_amc2: update to v2.0rc4
parent
936732fa
Changes
1
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1 changed file
with
16 additions
and
20 deletions
+16
-20
migen/build/platforms/sinara/sayma_amc2.py
migen/build/platforms/sinara/sayma_amc2.py
+16
-20
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migen/build/platforms/sinara/sayma_amc2.py
View file @
383512b4
...
...
@@ -60,22 +60,22 @@ _io = [
Subsignal
(
"cas_n"
,
Pins
(
"E16"
),
IOStandard
(
"SSTL15_DCI"
)),
Subsignal
(
"we_n"
,
Pins
(
"D16"
),
IOStandard
(
"SSTL15_DCI"
)),
Subsignal
(
"cs_n"
,
Pins
(
"G19"
),
IOStandard
(
"SSTL15_DCI"
)),
Subsignal
(
"dm"
,
Pins
(
"
F27 E26 D23 G24
"
),
Subsignal
(
"dm"
,
Pins
(
"
G21 D21 C24 A28
"
),
IOStandard
(
"SSTL15_DCI"
),
Misc
(
"DATA_RATE=DDR"
)),
Subsignal
(
"dq"
,
Pins
(
"
C28 B27 A27 C27 D28 E28 A28 D29
"
,
"
D25
C2
6
E2
5 B25 C24 A25 D24 B26
"
,
"
B20 D21
B2
2
E2
3 E22 D20 B21 A20
"
,
"
F23 H21 F24 G21 F22 E21 G22 E20
"
),
"
E20 G22 F25 F22 E21 F20 G24 G20
"
,
"
E22
C2
2
E2
3 A20 D23 B20 C23 C21
"
,
"
A25 E26
B2
4
E2
5 D25 D26 A24 B25
"
,
"
A29 E27 B29 F27 C27 D28 B27 C28
"
),
IOStandard
(
"SSTL15_DCI"
),
Misc
(
"ODT=RTT_40"
),
Misc
(
"DATA_RATE=DDR"
)),
Subsignal
(
"dqs_p"
,
Pins
(
"
B29 B24 C21 G20
"
),
Subsignal
(
"dqs_p"
,
Pins
(
"
F24 B22 B26 D29
"
),
IOStandard
(
"DIFF_SSTL15_DCI"
),
Misc
(
"ODT=RTT_40"
),
Misc
(
"DATA_RATE=DDR"
)),
Subsignal
(
"dqs_n"
,
Pins
(
"
A29 A24 C22 F20
"
),
Subsignal
(
"dqs_n"
,
Pins
(
"
F23 B21 C26 E28
"
),
IOStandard
(
"DIFF_SSTL15_DCI"
),
Misc
(
"ODT=RTT_40"
),
Misc
(
"DATA_RATE=DDR"
)),
...
...
@@ -146,12 +146,12 @@ _io = [
),
(
"sma_io"
,
0
,
Subsignal
(
"level"
,
Pins
(
"
K23
"
)),
Subsignal
(
"level"
,
Pins
(
"
P26
"
)),
Subsignal
(
"direction"
,
Pins
(
"K25"
)),
IOStandard
(
"LVCMOS33"
)
),
(
"sma_io"
,
1
,
Subsignal
(
"level"
,
Pins
(
"
L25
"
)),
Subsignal
(
"level"
,
Pins
(
"
N24
"
)),
Subsignal
(
"direction"
,
Pins
(
"L23"
)),
IOStandard
(
"LVCMOS33"
)
),
...
...
@@ -171,8 +171,8 @@ _io = [
Subsignal
(
"int"
,
Pins
(
"L22"
),
IOStandard
(
"LVCMOS33"
))
),
(
"si5324_clkin"
,
0
,
Subsignal
(
"p"
,
Pins
(
"
D13
"
)),
Subsignal
(
"n"
,
Pins
(
"
C13
"
)),
Subsignal
(
"p"
,
Pins
(
"
AE27
"
)),
Subsignal
(
"n"
,
Pins
(
"
AF27
"
)),
IOStandard
(
"LVDS"
),
),
# TODO: rename, this is now muxed with the WR PLL
...
...
@@ -217,10 +217,6 @@ _io = [
Subsignal
(
"p"
,
Pins
(
"V6"
)),
Subsignal
(
"n"
,
Pins
(
"V5"
)),
),
(
"dac_refclk"
,
1
,
Subsignal
(
"p"
,
Pins
(
"P6"
)),
Subsignal
(
"n"
,
Pins
(
"P5"
)),
),
(
"dac_sysref"
,
0
,
Subsignal
(
"p"
,
Pins
(
"B10"
)),
Subsignal
(
"n"
,
Pins
(
"A10"
)),
...
...
@@ -320,17 +316,17 @@ _io = [
),
]
# differences with Sayma v1: CLK1_M2C, DP0_M2C, GBTCLK0_M2C, LA08
# differences with Sayma v1: CLK1_M2C,
DP0_C2M,
DP0_M2C, GBTCLK0_M2C, LA08
_connectors
=
[
(
"LPC"
,
{
"CLK0_M2C_N"
:
"AA25"
,
"CLK0_M2C_P"
:
"AA24"
,
"CLK1_M2C_N"
:
"AC32"
,
"CLK1_M2C_P"
:
"AC31"
,
"DP0_C2M_N"
:
"A
F28
"
,
"DP0_C2M_P"
:
"A
E28
"
,
"DP0_M2C_N"
:
"A
C32
"
,
"DP0_M2C_P"
:
"A
C31
"
,
"DP0_C2M_N"
:
"A
N16
"
,
"DP0_C2M_P"
:
"A
M17
"
,
"DP0_M2C_N"
:
"A
P18
"
,
"DP0_M2C_P"
:
"A
N19
"
,
"GBTCLK0_M2C_N"
:
"AH17"
,
"GBTCLK0_M2C_P"
:
"AH18"
,
"LA00_CC_N"
:
"AB32"
,
...
...
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