Commit 36f7e18a authored by Astro's avatar Astro Committed by Sébastien Bourdeauducq
Browse files

xilinx: add copy_ips()

parent f56ba262
import os
import shutil
from migen.build.generic_platform import GenericPlatform
from migen.build.xilinx import common, vivado, ise
......@@ -24,6 +25,19 @@ class XilinxPlatform(GenericPlatform):
def add_ip(self, filename):
self.ips.add((os.path.abspath(filename)))
def copy_ips(self, build_dir, subdir="ip"):
copied_ips = set()
target = os.path.join(build_dir, subdir)
os.makedirs(target, exist_ok=True)
for filename in self.ips:
path = os.path.join(subdir, os.path.basename(filename))
dest = os.path.join(build_dir, path)
shutil.copyfile(filename, dest)
copied_ips.add(path)
return copied_ips
def get_verilog(self, *args, special_overrides=dict(), **kwargs):
so = dict(common.xilinx_special_overrides)
if self.device[:3] == "xc6":
......
......@@ -211,7 +211,7 @@ class XilinxVivadoToolchain:
v_output.write(v_file)
sources = platform.copy_sources(build_dir) | {(v_file, "verilog", "work")}
edifs = platform.edifs
ips = platform.ips
ips = platform.copy_ips(build_dir)
self._build_batch(platform, sources, edifs, ips, build_name, build_dir)
tools.write_to_file(build_name + ".xdc", _build_xdc(named_sc, named_pc))
if run:
......
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