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Kestrel Collaboration
Kestrel LiteX
migen
Commits
3143608e
Commit
3143608e
authored
12 years ago
by
Sebastien Bourdeauducq
Browse files
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examples/wb_intercon: update to new APIs
parent
6a9b5978
Changes
4
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Showing
4 changed files
with
109 additions
and
109 deletions
+109
-109
examples/wb_intercon/intercon_conv.py
examples/wb_intercon/intercon_conv.py
+4
-4
examples/wb_intercon/master.v
examples/wb_intercon/master.v
+2
-2
examples/wb_intercon/slave.v
examples/wb_intercon/slave.v
+1
-1
examples/wb_intercon/tb_intercon.v
examples/wb_intercon/tb_intercon.v
+102
-102
No files found.
examples/wb_intercon/intercon_conv.py
View file @
3143608e
from
migen.fhdl
import
verilog
from
migen.fhdl
import
verilog
from
migen.bus
import
wishbone
from
migen.bus
import
wishbone
m1
=
wishbone
.
Master
(
"m1"
)
m1
=
wishbone
.
Master
()
m2
=
wishbone
.
Master
(
"m2"
)
m2
=
wishbone
.
Master
()
s1
=
wishbone
.
Slave
(
"s1"
)
s1
=
wishbone
.
Slave
()
s2
=
wishbone
.
Slave
(
"s2"
)
s2
=
wishbone
.
Slave
()
wishbonecon0
=
wishbone
.
InterconnectShared
(
wishbonecon0
=
wishbone
.
InterconnectShared
(
[
m1
,
m2
],
[
m1
,
m2
],
[(
0
,
s1
),
(
1
,
s2
)],
[(
0
,
s1
),
(
1
,
s2
)],
...
...
This diff is collapsed.
Click to expand it.
examples/wb_intercon/master.v
View file @
3143608e
...
@@ -26,7 +26,7 @@ module master #(
...
@@ -26,7 +26,7 @@ module master #(
output
reg
[
31
:
0
]
dat_w
,
output
reg
[
31
:
0
]
dat_w
,
input
[
31
:
0
]
dat_r
,
input
[
31
:
0
]
dat_r
,
output
reg
[
31
:
0
]
adr
,
output
reg
[
29
:
0
]
adr
,
output
reg
we
,
output
reg
we
,
output
reg
[
3
:
0
]
sel
,
output
reg
[
3
:
0
]
sel
,
output
cyc
,
output
cyc
,
...
@@ -66,7 +66,7 @@ always @(posedge sys_clk) begin
...
@@ -66,7 +66,7 @@ always @(posedge sys_clk) begin
active
<=
1'b0
;
active
<=
1'b0
;
end
else
if
(
~
active
)
begin
end
else
if
(
~
active
)
begin
if
(($
random
%
p
)
==
0
)
begin
if
(($
random
%
p
)
==
0
)
begin
adr
<=
(($
random
%
5
)
<<
(
3
2
-
2
))
+
id
;
adr
<=
(($
random
%
5
)
<<
(
3
0
-
2
))
+
id
;
sel
<=
sel
+
1
;
sel
<=
sel
+
1
;
active
<=
1'b1
;
active
<=
1'b1
;
if
(($
random
%
2
)
==
0
)
begin
if
(($
random
%
2
)
==
0
)
begin
...
...
This diff is collapsed.
Click to expand it.
examples/wb_intercon/slave.v
View file @
3143608e
...
@@ -24,7 +24,7 @@ module slave #(
...
@@ -24,7 +24,7 @@ module slave #(
input
[
31
:
0
]
dat_w
,
input
[
31
:
0
]
dat_w
,
output
reg
[
31
:
0
]
dat_r
,
output
reg
[
31
:
0
]
dat_r
,
input
[
31
:
0
]
adr
,
input
[
29
:
0
]
adr
,
input
we
,
input
we
,
input
[
3
:
0
]
sel
,
input
[
3
:
0
]
sel
,
input
cyc
,
input
cyc
,
...
...
This diff is collapsed.
Click to expand it.
examples/wb_intercon/tb_intercon.v
View file @
3143608e
/*
/*
* Milkymist SoC
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2011 Sebastien Bourdeauducq
* Copyright (C) 2007, 2008, 2009, 2011
, 2012
Sebastien Bourdeauducq
*
*
* This program is free software: you can redistribute it and/or modify
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* it under the terms of the GNU General Public License as published by
...
@@ -23,54 +23,54 @@ reg sys_clk;
...
@@ -23,54 +23,54 @@ reg sys_clk;
//------------------------------------------------------------------
//------------------------------------------------------------------
// Wishbone master wires
// Wishbone master wires
//------------------------------------------------------------------
//------------------------------------------------------------------
wire
[
31
:
0
]
wishbone_
m1_
adr
,
wire
[
29
:
0
]
m1_
wishbone_adr
,
wishbone_
m2_
adr
;
m2_
wishbone_adr
;
wire
[
31
:
0
]
wishbone_
m1_
dat_r
,
wire
[
31
:
0
]
m1_
wishbone_dat_r
,
wishbone_
m1_
dat_w
,
m1_
wishbone_dat_w
,
wishbone_
m2_
dat_r
,
m2_
wishbone_dat_r
,
wishbone_
m2_
dat_w
;
m2_
wishbone_dat_w
;
wire
[
3
:
0
]
wishbone_
m1_
sel
,
wire
[
3
:
0
]
m1_
wishbone_sel
,
wishbone_
m2_
sel
;
m2_
wishbone_sel
;
wire
wishbone_
m1_
we
,
wire
m1_
wishbone_we
,
wishbone_
m2_
we
;
m2_
wishbone_we
;
wire
wishbone_
m1_
cyc
,
wire
m1_
wishbone_cyc
,
wishbone_
m2_
cyc
;
m2_
wishbone_cyc
;
wire
wishbone_
m1_
stb
,
wire
m1_
wishbone_stb
,
wishbone_
m2_
stb
;
m2_
wishbone_stb
;
wire
wishbone_
m1_
ack
,
wire
m1_
wishbone_ack
,
wishbone_
m2_
ack
;
m2_
wishbone_ack
;
//------------------------------------------------------------------
//------------------------------------------------------------------
// Wishbone slave wires
// Wishbone slave wires
//------------------------------------------------------------------
//------------------------------------------------------------------
wire
[
31
:
0
]
wishbone_
s1_
adr
,
wire
[
29
:
0
]
s1_
wishbone_adr
,
wishbone_
s2_
adr
;
s2_
wishbone_adr
;
wire
[
31
:
0
]
wishbone_
s1_
dat_r
,
wire
[
31
:
0
]
s1_
wishbone_dat_r
,
wishbone_
s1_
dat_w
,
s1_
wishbone_dat_w
,
wishbone_
s2_
dat_r
,
s2_
wishbone_dat_r
,
wishbone_
s2_
dat_w
;
s2_
wishbone_dat_w
;
wire
[
3
:
0
]
wishbone_
s1_
sel
,
wire
[
3
:
0
]
s1_
wishbone_sel
,
wishbone_
s2_
sel
;
s2_
wishbone_sel
;
wire
wishbone_
s1_
we
,
wire
s1_
wishbone_we
,
wishbone_
s2_
we
;
s2_
wishbone_we
;
wire
wishbone_
s1_
cyc
,
wire
s1_
wishbone_cyc
,
wishbone_
s2_
cyc
;
s2_
wishbone_cyc
;
wire
wishbone_
s1_
stb
,
wire
s1_
wishbone_stb
,
wishbone_
s2_
stb
;
s2_
wishbone_stb
;
wire
wishbone_
s1_
ack
,
wire
s1_
wishbone_ack
,
wishbone_
s2_
ack
;
s2_
wishbone_ack
;
//---------------------------------------------------------------------------
//---------------------------------------------------------------------------
// Wishbone switch
// Wishbone switch
...
@@ -80,84 +80,84 @@ intercon dut(
...
@@ -80,84 +80,84 @@ intercon dut(
.
sys_rst
(
sys_rst
),
.
sys_rst
(
sys_rst
),
// Master 0
// Master 0
.
wishbone_
m1_
dat_o
(
wishbone_
m1_
dat_w
),
.
m1_
wishbone_dat_o
(
m1_
wishbone_dat_w
),
.
wishbone_
m1_
dat_i
(
wishbone_
m1_
dat_r
),
.
m1_
wishbone_dat_i
(
m1_
wishbone_dat_r
),
.
wishbone_
m1_
adr_o
(
wishbone_
m1_
adr
),
.
m1_
wishbone_adr_o
(
m1_
wishbone_adr
),
.
wishbone_
m1_
we_o
(
wishbone_
m1_
we
),
.
m1_
wishbone_we_o
(
m1_
wishbone_we
),
.
wishbone_
m1_
sel_o
(
wishbone_
m1_
sel
),
.
m1_
wishbone_sel_o
(
m1_
wishbone_sel
),
.
wishbone_
m1_
cyc_o
(
wishbone_
m1_
cyc
),
.
m1_
wishbone_cyc_o
(
m1_
wishbone_cyc
),
.
wishbone_
m1_
stb_o
(
wishbone_
m1_
stb
),
.
m1_
wishbone_stb_o
(
m1_
wishbone_stb
),
.
wishbone_
m1_
ack_i
(
wishbone_
m1_
ack
),
.
m1_
wishbone_ack_i
(
m1_
wishbone_ack
),
// Master 1
// Master 1
.
wishbone_
m2_
dat_o
(
wishbone_
m2_
dat_w
),
.
m2_
wishbone_dat_o
(
m2_
wishbone_dat_w
),
.
wishbone_
m2_
dat_i
(
wishbone_
m2_
dat_r
),
.
m2_
wishbone_dat_i
(
m2_
wishbone_dat_r
),
.
wishbone_
m2_
adr_o
(
wishbone_
m2_
adr
),
.
m2_
wishbone_adr_o
(
m2_
wishbone_adr
),
.
wishbone_
m2_
we_o
(
wishbone_
m2_
we
),
.
m2_
wishbone_we_o
(
m2_
wishbone_we
),
.
wishbone_
m2_
sel_o
(
wishbone_
m2_
sel
),
.
m2_
wishbone_sel_o
(
m2_
wishbone_sel
),
.
wishbone_
m2_
cyc_o
(
wishbone_
m2_
cyc
),
.
m2_
wishbone_cyc_o
(
m2_
wishbone_cyc
),
.
wishbone_
m2_
stb_o
(
wishbone_
m2_
stb
),
.
m2_
wishbone_stb_o
(
m2_
wishbone_stb
),
.
wishbone_
m2_
ack_i
(
wishbone_
m2_
ack
),
.
m2_
wishbone_ack_i
(
m2_
wishbone_ack
),
// Slave 0
// Slave 0
.
wishbone_
s1_
dat_o
(
wishbone_
s1_
dat_r
),
.
s1_
wishbone_dat_o
(
s1_
wishbone_dat_r
),
.
wishbone_
s1_
dat_i
(
wishbone_
s1_
dat_w
),
.
s1_
wishbone_dat_i
(
s1_
wishbone_dat_w
),
.
wishbone_
s1_
adr_i
(
wishbone_
s1_
adr
),
.
s1_
wishbone_adr_i
(
s1_
wishbone_adr
),
.
wishbone_
s1_
sel_i
(
wishbone_
s1_
sel
),
.
s1_
wishbone_sel_i
(
s1_
wishbone_sel
),
.
wishbone_
s1_
we_i
(
wishbone_
s1_
we
),
.
s1_
wishbone_we_i
(
s1_
wishbone_we
),
.
wishbone_
s1_
cyc_i
(
wishbone_
s1_
cyc
),
.
s1_
wishbone_cyc_i
(
s1_
wishbone_cyc
),
.
wishbone_
s1_
stb_i
(
wishbone_
s1_
stb
),
.
s1_
wishbone_stb_i
(
s1_
wishbone_stb
),
.
wishbone_
s1_
ack_o
(
wishbone_
s1_
ack
),
.
s1_
wishbone_ack_o
(
s1_
wishbone_ack
),
// Slave 1
// Slave 1
.
wishbone_
s2_
dat_o
(
wishbone_
s2_
dat_r
),
.
s2_
wishbone_dat_o
(
s2_
wishbone_dat_r
),
.
wishbone_
s2_
dat_i
(
wishbone_
s2_
dat_w
),
.
s2_
wishbone_dat_i
(
s2_
wishbone_dat_w
),
.
wishbone_
s2_
adr_i
(
wishbone_
s2_
adr
),
.
s2_
wishbone_adr_i
(
s2_
wishbone_adr
),
.
wishbone_
s2_
sel_i
(
wishbone_
s2_
sel
),
.
s2_
wishbone_sel_i
(
s2_
wishbone_sel
),
.
wishbone_
s2_
we_i
(
wishbone_
s2_
we
),
.
s2_
wishbone_we_i
(
s2_
wishbone_we
),
.
wishbone_
s2_
cyc_i
(
wishbone_
s2_
cyc
),
.
s2_
wishbone_cyc_i
(
s2_
wishbone_cyc
),
.
wishbone_
s2_
stb_i
(
wishbone_
s2_
stb
),
.
s2_
wishbone_stb_i
(
s2_
wishbone_stb
),
.
wishbone_
s2_
ack_o
(
wishbone_
s2_
ack
)
.
s2_
wishbone_ack_o
(
s2_
wishbone_ack
)
);
);
//---------------------------------------------------------------------------
//---------------------------------------------------------------------------
// Masters
// Masters
//---------------------------------------------------------------------------
//---------------------------------------------------------------------------
wire
wishbone_
m1_
end
;
wire
m1_
wishbone_end
;
master
#(
master
#(
.
id
(
0
)
.
id
(
0
)
)
m0
(
)
m0
(
.
sys_clk
(
sys_clk
),
.
sys_clk
(
sys_clk
),
.
sys_rst
(
sys_rst
),
.
sys_rst
(
sys_rst
),
.
dat_w
(
wishbone_
m1_
dat_w
),
.
dat_w
(
m1_
wishbone_dat_w
),
.
dat_r
(
wishbone_
m1_
dat_r
),
.
dat_r
(
m1_
wishbone_dat_r
),
.
adr
(
wishbone_
m1_
adr
),
.
adr
(
m1_
wishbone_adr
),
.
we
(
wishbone_
m1_
we
),
.
we
(
m1_
wishbone_we
),
.
sel
(
wishbone_
m1_
sel
),
.
sel
(
m1_
wishbone_sel
),
.
cyc
(
wishbone_
m1_
cyc
),
.
cyc
(
m1_
wishbone_cyc
),
.
stb
(
wishbone_
m1_
stb
),
.
stb
(
m1_
wishbone_stb
),
.
ack
(
wishbone_
m1_
ack
),
.
ack
(
m1_
wishbone_ack
),
.
tend
(
wishbone_
m1_
end
)
.
tend
(
m1_
wishbone_end
)
);
);
wire
wishbone_
m2_
end
;
wire
m2_
wishbone_end
;
master
#(
master
#(
.
id
(
1
)
.
id
(
1
)
)
m1
(
)
m1
(
.
sys_clk
(
sys_clk
),
.
sys_clk
(
sys_clk
),
.
sys_rst
(
sys_rst
),
.
sys_rst
(
sys_rst
),
.
dat_w
(
wishbone_
m2_
dat_w
),
.
dat_w
(
m2_
wishbone_dat_w
),
.
dat_r
(
wishbone_
m2_
dat_r
),
.
dat_r
(
m2_
wishbone_dat_r
),
.
adr
(
wishbone_
m2_
adr
),
.
adr
(
m2_
wishbone_adr
),
.
we
(
wishbone_
m2_
we
),
.
we
(
m2_
wishbone_we
),
.
sel
(
wishbone_
m2_
sel
),
.
sel
(
m2_
wishbone_sel
),
.
cyc
(
wishbone_
m2_
cyc
),
.
cyc
(
m2_
wishbone_cyc
),
.
stb
(
wishbone_
m2_
stb
),
.
stb
(
m2_
wishbone_stb
),
.
ack
(
wishbone_
m2_
ack
),
.
ack
(
m2_
wishbone_ack
),
.
tend
(
wishbone_
m2_
end
)
.
tend
(
m2_
wishbone_end
)
);
);
//---------------------------------------------------------------------------
//---------------------------------------------------------------------------
...
@@ -170,14 +170,14 @@ slave #(
...
@@ -170,14 +170,14 @@ slave #(
.
sys_clk
(
sys_clk
),
.
sys_clk
(
sys_clk
),
.
sys_rst
(
sys_rst
),
.
sys_rst
(
sys_rst
),
.
dat_w
(
wishbone_
s1_
dat_w
),
.
dat_w
(
s1_
wishbone_dat_w
),
.
dat_r
(
wishbone_
s1_
dat_r
),
.
dat_r
(
s1_
wishbone_dat_r
),
.
adr
(
wishbone_
s1_
adr
),
.
adr
(
s1_
wishbone_adr
),
.
we
(
wishbone_
s1_
we
),
.
we
(
s1_
wishbone_we
),
.
sel
(
wishbone_
s1_
sel
),
.
sel
(
s1_
wishbone_sel
),
.
cyc
(
wishbone_
s1_
cyc
),
.
cyc
(
s1_
wishbone_cyc
),
.
stb
(
wishbone_
s1_
stb
),
.
stb
(
s1_
wishbone_stb
),
.
ack
(
wishbone_
s1_
ack
)
.
ack
(
s1_
wishbone_ack
)
);
);
slave
#(
slave
#(
...
@@ -186,20 +186,20 @@ slave #(
...
@@ -186,20 +186,20 @@ slave #(
.
sys_clk
(
sys_clk
),
.
sys_clk
(
sys_clk
),
.
sys_rst
(
sys_rst
),
.
sys_rst
(
sys_rst
),
.
dat_w
(
wishbone_
s2_
dat_w
),
.
dat_w
(
s2_
wishbone_dat_w
),
.
dat_r
(
wishbone_
s2_
dat_r
),
.
dat_r
(
s2_
wishbone_dat_r
),
.
adr
(
wishbone_
s2_
adr
),
.
adr
(
s2_
wishbone_adr
),
.
we
(
wishbone_
s2_
we
),
.
we
(
s2_
wishbone_we
),
.
sel
(
wishbone_
s2_
sel
),
.
sel
(
s2_
wishbone_sel
),
.
cyc
(
wishbone_
s2_
cyc
),
.
cyc
(
s2_
wishbone_cyc
),
.
stb
(
wishbone_
s2_
stb
),
.
stb
(
s2_
wishbone_stb
),
.
ack
(
wishbone_
s2_
ack
)
.
ack
(
s2_
wishbone_ack
)
);
);
initial
sys_clk
=
1'b0
;
initial
sys_clk
=
1'b0
;
always
#
5
sys_clk
=
~
sys_clk
;
always
#
5
sys_clk
=
~
sys_clk
;
wire
all_end
=
wishbone_
m1_
end
&
wishbone_
m2_
end
;
wire
all_end
=
m1_
wishbone_end
&
m2_
wishbone_end
;
always
begin
always
begin
$
dumpfile
(
"intercon.vcd"
);
$
dumpfile
(
"intercon.vcd"
);
...
...
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