Commit 1eb348c5 authored by Sebastien Bourdeauducq's avatar Sebastien Bourdeauducq
Browse files

fhdl: do not attempt slicing non-array signals to keep Verilog happy

parent fcd6583c
...@@ -34,6 +34,12 @@ def _printexpr(ns, node): ...@@ -34,6 +34,12 @@ def _printexpr(ns, node):
raise TypeError raise TypeError
return "(" + r + ")" return "(" + r + ")"
elif isinstance(node, _Slice): elif isinstance(node, _Slice):
# Verilog does not like us slicing non-array signals...
if isinstance(node.value, Signal) \
and node.value.bv.width == 1 \
and node.start == 0 and node.stop == 1:
return _printexpr(ns, node.value)
if node.start + 1 == node.stop: if node.start + 1 == node.stop:
sr = "[" + str(node.start) + "]" sr = "[" + str(node.start) + "]"
else: else:
......
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