Skip to content
GitLab
Projects
Groups
Snippets
Help
Loading...
Help
Help
Support
Community forum
Keyboard shortcuts
?
Submit feedback
Contribute to GitLab
Sign in / Register
Toggle navigation
Open sidebar
Kestrel Collaboration
Kestrel LiteX
migen
Commits
1eb348c5
Commit
1eb348c5
authored
12 years ago
by
Sebastien Bourdeauducq
Browse files
Options
Download
Email Patches
Plain Diff
fhdl: do not attempt slicing non-array signals to keep Verilog happy
parent
fcd6583c
Changes
1
Hide whitespace changes
Inline
Side-by-side
Showing
1 changed file
with
6 additions
and
0 deletions
+6
-0
migen/fhdl/verilog.py
migen/fhdl/verilog.py
+6
-0
No files found.
migen/fhdl/verilog.py
View file @
1eb348c5
...
@@ -34,6 +34,12 @@ def _printexpr(ns, node):
...
@@ -34,6 +34,12 @@ def _printexpr(ns, node):
raise
TypeError
raise
TypeError
return
"("
+
r
+
")"
return
"("
+
r
+
")"
elif
isinstance
(
node
,
_Slice
):
elif
isinstance
(
node
,
_Slice
):
# Verilog does not like us slicing non-array signals...
if
isinstance
(
node
.
value
,
Signal
)
\
and
node
.
value
.
bv
.
width
==
1
\
and
node
.
start
==
0
and
node
.
stop
==
1
:
return
_printexpr
(
ns
,
node
.
value
)
if
node
.
start
+
1
==
node
.
stop
:
if
node
.
start
+
1
==
node
.
stop
:
sr
=
"["
+
str
(
node
.
start
)
+
"]"
sr
=
"["
+
str
(
node
.
start
)
+
"]"
else
:
else
:
...
...
This diff is collapsed.
Click to expand it.
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
.
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment