Commit 1ce4fbdb authored by Sebastien Bourdeauducq's avatar Sebastien Bourdeauducq
Browse files

example: flow conversion

parent edf90870
from migen.fhdl import verilog
from migen.flow.ala import *
act = Divider(32)
frag = act.get_control_fragment() + act.get_process_fragment()
print(verilog.Convert(frag))
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