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Kestrel Collaboration
Kestrel LiteX
migen
Commits
19ca7d8d
Commit
19ca7d8d
authored
6 years ago
by
William D. Jones
Committed by
whitequark
6 years ago
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platforms/tinyfpga_b: Add default serial mapping.
parent
cba5bea5
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migen/build/platforms/tinyfpga_b.py
migen/build/platforms/tinyfpga_b.py
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migen/build/platforms/tinyfpga_b.py
View file @
19ca7d8d
...
@@ -28,6 +28,16 @@ _connectors = [
...
@@ -28,6 +28,16 @@ _connectors = [
]
]
# Default peripherals
serial
=
[
(
"serial"
,
0
,
Subsignal
(
"tx"
,
Pins
(
"GPIO:0"
)),
Subsignal
(
"rx"
,
Pins
(
"GPIO:1"
)),
IOStandard
(
"LVCMOS33"
)
)
]
class
Platform
(
LatticePlatform
):
class
Platform
(
LatticePlatform
):
default_clk_name
=
"clk16"
default_clk_name
=
"clk16"
default_clk_period
=
62.5
default_clk_period
=
62.5
...
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