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Kestrel Collaboration
Kestrel LiteX
migen
Commits
076c171c
Commit
076c171c
authored
12 years ago
by
Sebastien Bourdeauducq
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Use meaningful class names
parent
d3d5b481
Changes
7
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Showing
7 changed files
with
9 additions
and
9 deletions
+9
-9
examples/corelogic_conv.py
examples/corelogic_conv.py
+2
-2
migen/bus/wishbone.py
migen/bus/wishbone.py
+1
-1
migen/bus/wishbone2csr.py
migen/bus/wishbone2csr.py
+2
-2
migen/corelogic/divider.py
migen/corelogic/divider.py
+1
-1
migen/corelogic/roundrobin.py
migen/corelogic/roundrobin.py
+1
-1
migen/corelogic/timeline.py
migen/corelogic/timeline.py
+1
-1
migen/flow/ala.py
migen/flow/ala.py
+1
-1
No files found.
examples/corelogic_conv.py
View file @
076c171c
from
migen.fhdl
import
verilog
from
migen.fhdl
import
verilog
from
migen.corelogic
import
divider
from
migen.corelogic
import
divider
d1
=
divider
.
Inst
(
16
)
d1
=
divider
.
Divider
(
16
)
d2
=
divider
.
Inst
(
16
)
d2
=
divider
.
Divider
(
16
)
frag
=
d1
.
get_fragment
()
+
d2
.
get_fragment
()
frag
=
d1
.
get_fragment
()
+
d2
.
get_fragment
()
o
=
verilog
.
convert
(
frag
,
{
o
=
verilog
.
convert
(
frag
,
{
d1
.
ready_o
,
d1
.
quotient_o
,
d1
.
remainder_o
,
d1
.
start_i
,
d1
.
dividend_i
,
d1
.
divisor_i
,
d1
.
ready_o
,
d1
.
quotient_o
,
d1
.
remainder_o
,
d1
.
start_i
,
d1
.
dividend_i
,
d1
.
divisor_i
,
...
...
This diff is collapsed.
Click to expand it.
migen/bus/wishbone.py
View file @
076c171c
...
@@ -29,7 +29,7 @@ class Arbiter:
...
@@ -29,7 +29,7 @@ class Arbiter:
def
__init__
(
self
,
masters
,
target
):
def
__init__
(
self
,
masters
,
target
):
self
.
masters
=
masters
self
.
masters
=
masters
self
.
target
=
target
self
.
target
=
target
self
.
rr
=
roundrobin
.
Inst
(
len
(
self
.
masters
))
self
.
rr
=
roundrobin
.
RoundRobin
(
len
(
self
.
masters
))
def
get_fragment
(
self
):
def
get_fragment
(
self
):
comb
=
[]
comb
=
[]
...
...
This diff is collapsed.
Click to expand it.
migen/bus/wishbone2csr.py
View file @
076c171c
...
@@ -3,11 +3,11 @@ from migen.bus import csr
...
@@ -3,11 +3,11 @@ from migen.bus import csr
from
migen.fhdl.structure
import
*
from
migen.fhdl.structure
import
*
from
migen.corelogic
import
timeline
from
migen.corelogic
import
timeline
class
Inst
():
class
WB2CSR
():
def
__init__
(
self
):
def
__init__
(
self
):
self
.
wishbone
=
wishbone
.
Slave
(
"to_csr"
)
self
.
wishbone
=
wishbone
.
Slave
(
"to_csr"
)
self
.
csr
=
csr
.
Master
(
"from_wishbone"
)
self
.
csr
=
csr
.
Master
(
"from_wishbone"
)
self
.
timeline
=
timeline
.
Inst
(
self
.
wishbone
.
cyc_i
&
self
.
wishbone
.
stb_i
,
self
.
timeline
=
timeline
.
Timeline
(
self
.
wishbone
.
cyc_i
&
self
.
wishbone
.
stb_i
,
[(
1
,
[
self
.
csr
.
we_o
.
eq
(
self
.
wishbone
.
we_i
)]),
[(
1
,
[
self
.
csr
.
we_o
.
eq
(
self
.
wishbone
.
we_i
)]),
(
2
,
[
self
.
wishbone
.
ack_o
.
eq
(
1
)]),
(
2
,
[
self
.
wishbone
.
ack_o
.
eq
(
1
)]),
(
3
,
[
self
.
wishbone
.
ack_o
.
eq
(
0
)])])
(
3
,
[
self
.
wishbone
.
ack_o
.
eq
(
0
)])])
...
...
This diff is collapsed.
Click to expand it.
migen/corelogic/divider.py
View file @
076c171c
from
migen.fhdl.structure
import
*
from
migen.fhdl.structure
import
*
class
Inst
:
class
Divider
:
def
__init__
(
self
,
w
):
def
__init__
(
self
,
w
):
self
.
w
=
w
self
.
w
=
w
...
...
This diff is collapsed.
Click to expand it.
migen/corelogic/roundrobin.py
View file @
076c171c
from
migen.fhdl.structure
import
*
from
migen.fhdl.structure
import
*
class
Inst
:
class
RoundRobin
:
def
__init__
(
self
,
n
):
def
__init__
(
self
,
n
):
self
.
n
=
n
self
.
n
=
n
self
.
bn
=
bits_for
(
self
.
n
-
1
)
self
.
bn
=
bits_for
(
self
.
n
-
1
)
...
...
This diff is collapsed.
Click to expand it.
migen/corelogic/timeline.py
View file @
076c171c
from
migen.fhdl.structure
import
*
from
migen.fhdl.structure
import
*
class
Inst
:
class
Timeline
:
def
__init__
(
self
,
trigger
,
events
):
def
__init__
(
self
,
trigger
,
events
):
self
.
trigger
=
trigger
self
.
trigger
=
trigger
self
.
events
=
events
self
.
events
=
events
...
...
This diff is collapsed.
Click to expand it.
migen/flow/ala.py
View file @
076c171c
...
@@ -60,7 +60,7 @@ class NE(_SimpleBinary):
...
@@ -60,7 +60,7 @@ class NE(_SimpleBinary):
class
DivMod
(
Actor
):
class
DivMod
(
Actor
):
def
__init__
(
self
,
width
):
def
__init__
(
self
,
width
):
self
.
div
=
divider
.
Inst
(
width
)
self
.
div
=
divider
.
Divider
(
width
)
Actor
.
__init__
(
self
,
Actor
.
__init__
(
self
,
SchedulingModel
(
SchedulingModel
.
SEQUENTIAL
,
width
),
SchedulingModel
(
SchedulingModel
.
SEQUENTIAL
,
width
),
(
"operands"
,
Sink
,
[(
"dividend"
,
self
.
div
.
dividend_i
),
(
"divisor"
,
self
.
div
.
divisor_i
)]),
(
"operands"
,
Sink
,
[(
"dividend"
,
self
.
div
.
dividend_i
),
(
"divisor"
,
self
.
div
.
divisor_i
)]),
...
...
This diff is collapsed.
Click to expand it.
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